arXiv subjects

M. Kandemir

Publications and source records attributed to M. Kandemir.

6 recordsLinked to original sources

arXiv2025

Reconstruction of neutrino events in the Accelerator Neutrino Neutron Interaction Experiment: Part I

The Accelerator Neutrino Neutron Interaction Experiment (ANNIE) was designed to reconstruct neutrino events from the Fermilab Booster Neutrino Beam (BNB) with the parallel goals of measuring neutron production in interactions with oxygen and serving as a testbed for new technology. The ANNIE detector consists of a 26-ton water Cherenkov target tank instrumented with conventional photomultiplier tubes (PMTs), a downstream tracking muon spectrometer, and an upstream double wall of plastic scintillator to serve to veto charged particles incoming from neutrino events that occur upstream of the experimental setup. ANNIE has also deployed multiple Large-Area Picosecond PhotoDetectors (LAPPDs) and a test vessel of water-based liquid scintillator (WbLS). This paper describes the event reconstruction performance of the detector before implementation of these novel technologies, which will serve as a baseline against which their impact can be measured. That said, even the techniques used for event reconstruction using only the conventional PMT array and muon spectrometer are significantly different than those used in other water Cherenkov detectors due to the small size of ANNIE (which makes nanosecond-scale timing not as useful as in a large detector) and the availability of reconstruction information from the tracking muon spectrometer. We demonstrate that combining the information from these two elements into a single fit using only pattern recognition yields a muon vertex uncertainty of 60 cm, a directional uncertainty of 13.2 degrees, and energy reconstruction uncertainty of about 10\% for BNB muon neutrino Charged Current Zero Pion (CC0pi) events.

hep-ex↗

arXiv2025

First Light from Beam Neutrinos on an LAPPD in ANNIE

The Accelerator Neutrino Neutron Interaction Experiment (ANNIE) is both a physics experiment and a technology testbed for next-generation light-based neutrino detection. In this paper, we report the first demonstration of a fully integrated Large Area Picosecond Photodetector (LAPPD) operating in a running neutrino beam experiment. Particular focus is given to the design, commissioning, and successful deployment of the Packaged ANNIE LAPPD (PAL), a waterproof, self-triggering module incorporating fast waveform digitization and precision timing synchronized to the ANNIE detector subsystems. We identify beam-correlated LAPPD data frames consistent with charged-current neutrino interactions observed in multiple detector subsystems, establishing the first detection of neutrino-induced Cherenkov light with an LAPPD. These results validate the system-level performance of LAPPDs under realistic experimental conditions-including long-term stability, timing synchronization, and event matching with conventional PMT and muon detector systems-marking a critical step toward their deployment in future large-scale neutrino and particle detectors.

hep-ex↗

arXiv2007

Thermal-Aware Task Allocation and Scheduling for Embedded Systems

Temperature affects not only the reliability but also the performance, power, and cost of the embedded system. This paper proposes a thermal-aware task allocation and scheduling algorithm for embedded systems. The algorithm is used as a sub-routine for hardware/software co-synthesis to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first task allocation and scheduling algorithm that takes temperature into consideration.

cs.AR↗

arXiv2007

Reliability-Centric High-Level Synthesis

Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class citizen in system design. In particular, reliability decisions taken early in system design can have significant benefits in terms of design quality. Motivated by this observation, this paper presents a reliability-centric high-level synthesis approach that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several designs, and compared the results with those obtained by a prior proposal.

cs.AR↗

arXiv2007

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems

As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, and reliability. In particular, many modern embedded systems operate under tight memory space constraints. One way of satisfying these constraints is to compress executable code and data as much as possible. While research on code compression have studied efficient hardware and software based code strategies, many of these techniques do not take application behavior into account, that is, the same compression/decompression strategy is used irrespective of the application being optimized. This paper presents a code compression strategy based on control flow graph (CFG) representation of the embedded program. The idea is to start with a memory image wherein all basic blocks are compressed, and decompress only the blocks that are predicted to be needed in the near future. When the current access to a basic block is over, our approach also decides the point at which the block could be compressed. We propose several compression and decompression strategies that try to reduce memory requirements without excessively increasing the original instruction cycle counts.

cs.OH↗

arXiv2007

A Constraint Network Based Approach to Memory Layout Optimization

While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking dependences (legality issues) and transformation of all of the array references within the loop body indiscriminately (while some of the references can benefit from the transformation, others may not). As a result, data transformations, i.e., transformations that modify memory layout of array data instead of loop structure have been proposed. One of the problems associated with data transformations is the difficulty of selecting a memory layout for an array that is acceptable to the entire program (not just to a single loop). In this paper, we formulate the problem of determining the memory layouts of arrays as a constraint network, and explore several methods of solution in a systematic way. Our experiments provide strong support in favor of employing constraint processing, and point out future research directions.

cs.PL↗