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M. Kilpatrick

Publications and source records attributed to M. Kilpatrick.

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A Compact Low-level RF Control System for Advanced Concept Compact Electron Linear Accelerator

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF performance and size, weight and power consumption (SWaP). The compact LLRF solution employs the direct RF sampling technique of RFSoC, which samples the RF signals directly without any analogue up and down conversion. Compared with the conventional heterodyne based architecture used for LLRF system of linear accelerator (LINAC), the elimination of analogue mixers can significantly reduce the size and weight of the system, especially with LINAC requires a larger number of RF channels. Based on the requirements of ACCEL, a prototype LLRF platform has been developed, and the control schemes have been proposed. The prototype LLRF system demonstrated magnitude and phase fluctuation levels below 1% and 1 degree, on the flat top of a 2 microseconds RF pulse. The LLRF control schemes proposed for ACCEL are implemented with a prototype hardware platform. This paper will introduce the new compact LLRF solution and summarize a selection of experimental test results of the prototype itself and with the accelerating structure cavities designed for ACCEL.

physics.acc-ph

LLRF System Considerations for a Compact, Commercial C-band Accelerator using the AMD Xilinx RF-SoC

This work describes the LLRF and control system in use for a novel accelerator structure developed for a compact design operating in C-band developed by SLAC, with collaboration from RadiaBeam and RadiaSoft. This design is a pulsed RF/pulsed beam system that only provides minimal monitoring for control of each two-cavity pair. Available signals include only a forward and reflected signal for each pair; such a design requires careful consideration of calibration and power-on routines, as well an understanding of how to correct for disturbances caused by the entire RF signal chain, including a new SSA, klystron, and distribution system. An AMD Xilinx RF-SoC with a separate supervisory computer is the LLRF system core, with on-board pulse-to-pulse feedback corrections. This work presents the current status of the project, as well as obstacles and manufacturing plans from the viewpoint of developing for larger-volume manufacturing. This material is based upon work supported by the Defense Advanced Research Projects Agency under Contract Numbers 140D0423C0006 and 140D0423C0007. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.

physics.acc-ph