arXiv subjects

M. Vicente Barreto Pinto

Publications and source records attributed to M. Vicente Barreto Pinto.

11 recordsLinked to original sources

arXiv2024

Testbeam Characterization of a SiGe BiCMOS Monolithic Silicon Pixel Detector with Internal Gain Layer

A monolithic silicon pixel ASIC prototype, produced in 2024 as part of the Horizon 2020 MONOLITH ERC Advanced project, was tested with a 120 GeV/c pion beam. The ASIC features a matrix of hexagonal pixels with a 100 μm pitch, read by low-noise, high-speed front-end electronics built using 130 nm SiGe BiCMOS technology. It includes the PicoAD sensor, which employs a continuous, deep PN junction to generate avalanche gain. Data were taken across power densities from 0.05 to 2.6 W/cm2 and sensor bias voltages from 90 to 180 V. At the highest bias voltage, corresponding to an electron gain of 50, and maximum power density, an efficiency of (99.99 \pm 0.01)% was achieved. The time resolution at this working point was (24.3 \pm 0.2) ps before time-walk correction, improving to (12.1 \pm 0.3) ps after correction.

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arXiv2024

Testbeam results of irradiated SiGe BiCMOS monolithic silicon pixel detector without internal gain layer

Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 x 1016 neq/cm2, and then tested using a beam of 120 GeV/c pions. The ASIC contains a matrix of 100 μm pitch hexagonal pixels, readout out by low noise and very fast frontend electronics produced in a 130 nm SiGe BiCMOS technology process. The dependence on the proton fluence of the efficiency and the time resolution of this prototype was measured with the frontend electronics operated at a power density between 0.13 and 0.9 W/cm2. The testbeam data show that the detection efficiency of 99.96% measured at sensor bias voltage of 200 V before irradiation becomes 96.2% after a fluence of 1 x 1016 neq/cm2. An increase of the sensor bias voltage to 300 V provides an efficiency to 99.7% at that proton fluence. The timing resolution of 20 ps measured before irradiation rises for a proton fluence of 1 x 1016 neq/cm2 to 53 and 45 ps at HV = 200 and 300 V, respectively.

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arXiv2024

Time Resolution of a SiGe BiCMOS Monolithic Silicon Pixel Detector without Internal Gain Layer with a Femtosecond Laser

The time resolution of the second monolithic silicon pixel prototype produced for the MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. At the highest frontend power density tested of 2.7 W/cm2, the time resolution with the femtosecond laser pulses was found to be 45 ps for signals generated by 1200 electrons, and 3 ps in the case of 11k electrons, which corresponds approximately to 0.4 and 3.5 times the most probable value of the charge generated by a minimum-ionizing particle. The results were compared with testbeam data taken with the same prototype to evaluate the time jitter produced by the fluctuations of the charge collection.

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arXiv2023

Radiation Tolerance of SiGe BiCMOS Monolithic Silicon Pixel Detectors without Internal Gain Layer

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 x 10^14 n_eq /cm^2 . The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35 {^\circ}C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm^2, the time jitter of the most-probable signal amplitude was estimated to be 21 ps for proton fluence up to 6 x 10 n_eq/cm^2 and 57 ps at 1 x 10^16 n_eq/cm^2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 x 10^16 n_eq/cm^2.

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arXiv2023

20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer of 350 Ωcm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.

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arXiv2022

Pixel detector hybridisation with Anisotropic Conductive Films

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, and in general for small-scale applications, such interconnect technologies need to be suitable for the assembly of single-dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. This contribution presents recent results of a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The ACF interconnect technology replaces the solder bumps with conductive particles embedded in an adhesive film. The electro-mechanical connection between the sensor and the read-out chip is achieved via thermo-compression of the ACF using a flip-chip device bonder. A specific pad topology is required to enable the connection via conductive particles and create cavities into which excess epoxy can flow. This pixel-pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process that is also under development within the project. The ENIG and ACF processes are qualified with the Timepix3 ASIC and sensors, with 55 um pixel pitch and 14 um pad diameter. The ACF technology can also be used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the ENIG plating and ACF processes and presents recent results on Timepix3 hybrid assemblies.

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arXiv2022

Picosecond Avalanche Detector -- working principle and gain measurement with a proof-of-concept prototype

The Picosecond Avalanche Detector is a multi-junction silicon pixel detector based on a $\mathrm{(NP)_{drift}(NP)_{gain}}$ structure, devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamp capability. It uses a continuous junction deep inside the sensor volume to amplify the primary charge produced by ionizing radiation in a thin absorption layer. The signal is then induced by the secondary charges moving inside a thicker drift region. A proof-of-concept monolithic prototype, consisting of a matrix of hexagonal pixels with 100 $μ$m pitch, has been produced using the 130 nm SiGe BiCMOS process by IHP microelectronics. Measurements on probe station and with a $^{55}$Fe X-ray source show that the prototype is functional and displays avalanche gain up to a maximum electron gain of 23. A study of the avalanche characteristics, corroborated by TCAD simulations, indicates that space-charge effects due to the large primary charge produced by the conversion of X-rays from the $^{55}$Fe source limits the effective gain.

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arXiv2022

Testbeam Results of the Picosecond Avalanche Detector Proof-Of-Concept Prototype

The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 μm pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm^2, respectively. In this first prototype the time resolution depends significantly on the distance from the center of the pixel, varying at the highest power consumption measured between 13 ps at the center of the pixel and 25 ps in the inter-pixel region.

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arXiv2022

Efficiency and time resolution of monolithic silicon pixel detectors in SiGe BiCMOS technology

A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 $μ$m. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of $\left(99.9^{+0.1}_{-0.2}\right)$% was measured together with a time resolution of $(36.4 \pm 0.8)$ps at the highest preamplifier bias current working point of 150 $μ$A and at a sensor bias voltage of 160 V. The ASIC was also characterized at lower bias voltage and preamplifier current.

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arXiv2020

Charge Collection and Electrical Characterization of Neutron Irradiated Silicon Pad Detectors for the CMS High Granularity Calorimeter

The replacement of the existing endcap calorimeter in the Compact Muon Solenoid (CMS) detector for the high-luminosity LHC (HL-LHC), scheduled for 2027, will be a high granularity calorimeter. It will provide detailed position, energy, and timing information on electromagnetic and hadronic showers in the immense pileup of the HL-LHC. The High Granularity Calorimeter (HGCAL) will use 120-, 200-, and 300-$μ\textrm{m}$ thick silicon (Si) pad sensors as the main active material and will sustain 1-MeV neutron equivalent fluences up to about $10^{16}~\textrm{n}_\textrm{eq}\textrm{cm}^{-2}$. In order to address the performance degradation of the Si detectors caused by the intense radiation environment, irradiation campaigns of test diode samples from 8-inch and 6-inch wafers were performed in two reactors. Characterization of the electrical and charge collection properties after irradiation involved both bulk polarities for the three sensor thicknesses. Since the Si sensors will be operated at -30 $^\circ$C to reduce increasing bulk leakage current with fluence, the charge collection investigation of 30 irradiated samples was carried out with the infrared-TCT setup at -30 $^\circ$C. TCAD simulation results at the lower fluences are in close agreement with the experimental results and provide predictions of sensor performance for the lower fluence regions not covered by the experimental study. All investigated sensors display 60$\%$ or higher charge collection efficiency at their respective highest lifetime fluences when operated at 800 V, and display above 90$\%$ at the lowest fluence, at 600 V. The collected charge close to the fluence of $10^{16}~\textrm{n}_\textrm{eq}\textrm{cm}^{-2}$ exceeds 1 fC at voltages beyond 800 V.

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arXiv2016

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in the testbeam of the HV-CMOS sensor CCPDv4 at CERN. Preliminary results have shown that the test system is very versatile. Further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.

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