arXiv subjects

Markus Fras

Publications and source records attributed to Markus Fras.

5 recordsLinked to original sources

arXiv2026

ATLAS MDT TDC Simulations for LHC Run3 and HL-LHC

The Large Hadron Collider (LHC) started the Run 3 operation in 2022, and the peak instantaneous luminosity in Run 3 may reach 3 x 10^34 cm-2s-1. The ATLAS Monitored Drift Tube (MDT) chambers are the main component of the precision tracking system in the ATLAS muon spectrometer. It is important to understand any potential issues with the MDT Front-End (FE) readout electronics for an expected level-1 (L1) trigger rate of 100 kHz and a complex deadtime of over 5% for Run 3 operations. We use raw data collected in 2022 to emulate the expected hit rates in MDT chambers and perform a realistic simulation on the ATLAS Muon TDC (Time-to-Digital Converter) (AMT) chip with the current configuration. We study the AMT chip performances by analyzing the trigger/L1/readout buffer occupancies and hit loss fractions under different luminosities with L1 rate of 100 kHz by using the Modelsim software. The hit loss fraction of the hottest MDT chamber (BIL3C05) is lower than 5% due to FE readout, even at a luminosity of 5.01 x 10^34 cm-2s-1 with a deadtime of 5% and a L1 rate of 100 kHz, indicating that AMT can operate under Run 3 conditions without problems. The MDT trigger and readout electronics will be replaced for triggerless readout during High-Luminosity LHC (HL-LHC) runs. We also simulate the AMT behavior in the triggerless mode up to 7.44 x 10^34 cm-2s-1 and propose possible AMT configurations in case some FE electronics could not be replaced during the long shutdown 3 (LS3).

physics.ins-det↗

arXiv2019

Design and performance of a TDC ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within 40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement.

physics.ins-det↗

arXiv2018

Hardware Implementation of a Fast Algorithm for the Reconstruction of Muon Tracks in ATLAS Muon Drift-Tube Chambers for the First-Level Muon Trigger at the HL-LHC

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC where the instantaneous luminosity will exceed the LHC Run 1 instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the resistive plate and thin gap trigger chambers. This limitation can be overcome by including the data of the precision muon drift tube (MDT) chambers in the first level trigger decision. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic. In order to demonstrate the feasibility of reconstructing tracks in MDT chambers within the short available first-level trigger latency of about 3~$\mu$s we implemented a seeded Hough transform on the ARM Cortex A9 microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beam data recorded in CERN's Gamma Irradiation Facility. We could show that by using the ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4 floating point operations in parallel the challenging latency requirement can be matched.

physics.ins-det↗

arXiv2016

Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

physics.ins-det↗

arXiv2016

Optimisation of the Read-out Electronics of Muon Drift-Tube Chambers for Very High Background Rates at HL-LHC and Future Colliders

In the ATLAS Muon Spectrometer, Monitored Drift Tube (MDT) chambers and sMDT chambers with half of the tube diameter of the MDTs are used for precision muon track reconstruction. The sMDT chambers are designed for operation at high counting rates due to neutron and gamma background irradiation expected for the HL-LHC and future hadron colliders. The existing MDT read-out electronics uses bipolar signal shaping which causes an undershoot of opposite polarity and same charge after a signal pulse. At high counting rates and short electronics dead time used for the sMDTs, signal pulses pile up on the undershoot of preceding background pulses leading to a reduction of the signal amplitude and a jitter in the drift time measurement and, therefore, to a degradation of drift tube efficiency and spatial resolution. In order to further increase the rate capability of sMDT tubes, baseline restoration can be used in the read-out electronics to suppress the pile-up effects. A discrete bipolar shaping circuit with baseline restoration has been developed and used for reading out sMDT tubes under irradiation with a 24 MBq 90Sr source. The measurements results show a substantial improvement of the performance of the sMDT tubes at high counting rates.

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