arXiv subjects

Marwan Jalaleddine

Publications and source records attributed to Marwan Jalaleddine.

9 recordsLinked to original sources

arXiv2026

Enabling Fast Polar SC Decoding with IR-HARQ

To extend the applications of polar codes within next-generation wireless communication systems, it is essential to incorporate support for Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) schemes. For very high-throughput applications, Successive Cancellation (SC) decoding is particularly appealing for polar codes owing to its high area efficiency. In this paper, we propose modifications to SC decoders that employ special nodes to accelerate decoding. Our modifications enable the use of polar IR-HARQ with SC decoding for high throughput applications. Compared to the unmodified SC IR-HARQ scheme, our proposed approach allows us to achieve a 72% reduction in node traversals with a polar code of length 2048. Simulation results confirm that the proposed special node modifications do not cause any degradation in FER performance.

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arXiv2026

A Universal Systematic Method to Generate Error Patterns on Memoryless Channels

The high computational cost of approaching the performance of Maximum-likelihood (ML) decoding has limited its practical use for decades. Because the complexity grows exponentially with the message length, researchers have spent years developing algorithms like Ordered Statistics Decoding (OSD), Partial Ordered Statistics Decoding (POSD) and Guessing Random Additive Noise decoding (GRAND) which try to approach ML performance. OSD, POSD and GRAND work by trying to guess the error patterns affecting the received signals. However, there does not exist a systematic method to extend the error pattern guesses to novel channels. This work introduces a systematic method that uses the Probability Density Function (PDF) of a memoryless channel to generate a set of error patterns that can be applied on any future received signal on this channel. Simulation results show that our proposed method applied on GRAND, OSD and POSD generally matches or outperforms current pre-generated error patterns on additive white Gaussian noise (AWGN) channel, mixture of Gaussian distribution channels, Rayleigh fading channel with perfect knowledge of Channel State Information (CSI) and Rayleigh fading channel with no perfect knowledge of Channel State Information (NCSI).

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arXiv2025

Hardware-friendly IR-HARQ for Polar SCL Decoders

To extend the applications of polar codes within next-generation wireless communication systems, it is essential to incorporate support for Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) schemes. The baseline IR-HARQ scheme's reliance on set-based operations leads to irregular memory access patterns, posing significant challenges for efficient hardware implementation. Furthermore, the introduction of new bit types increases the number of fast nodes that are decoded without traversing the sub-tree, resulting in a substantial area overhead when implemented in hardware. To address these issues and improve hardware compatibility, we propose transforming the set-based operations within the polar IR-HARQ scheme into binary vector operations. Additionally, we introduce a new fast node integration approach that avoids increasing the number of fast nodes, thereby minimizing the associated area overhead. Our proposed scheme results in a memory overhead of 25-27% compared to successive cancellation list (SCL) decoding without IR-HARQ support.

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arXiv2023

Step-GRAND: A Low Latency Universal Soft-input Decoder

GRAND features both soft-input and hard-input variants that are well suited to efficient hardware implementations that can be characterized with achievable average and worst-case decoding latency. This paper introduces step-GRAND, a soft-input variant of GRAND that, in addition to achieving appealing average decoding latency, also reduces the worst-case decoding latency of the corresponding hardware implementation. The hardware implementation results demonstrate that the proposed step-GRAND can decode CA-polar code $(128,105+11)$ with an average information throughput of $47.7$ Gbps at the target FER of $\leq10^{-7}$. Furthermore, the proposed step-GRAND hardware is $10\times$ more area efficient than the previous soft-input ORBGRAND hardware implementation, and its worst-case latency is $\frac{1}{6.8}\times$ that of the previous ORBGRAND hardware.

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arXiv2022

List-GRAND: A practical way to achieve Maximum Likelihood Decoding

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed universal Maximum Likelihood (ML) decoder for short-length and high-rate linear block-codes. Soft-GRAND (SGRAND) is a prominent soft-input GRAND variant, outperforming the other GRAND variants in decoding performance; nevertheless, SGRAND is not suitable for parallel hardware implementation. Ordered Reliability Bits-GRAND (ORBGRAND) is another soft-input GRAND variant that is suitable for parallel hardware implementation, however it has lower decoding performance than SGRAND. In this paper, we propose List-GRAND (LGRAND), a technique for enhancing the decoding performance of ORBGRAND to match the ML decoding performance of SGRAND. Numerical simulation results show that LGRAND enhances ORBGRAND's decoding performance by $0.5-0.75$ dB for channel-codes of various classes at a target FER of $10^{-7}$. For linear block codes of length $127/128$ and different code-rates, LGRAND's VLSI implementation can achieve an average information throughput of $47.27-51.36$ Gbps. In comparison to ORBGRAND's VLSI implementation, the proposed LGRAND hardware has a $4.84\%$ area overhead.

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arXiv2022

GRAND for Rayleigh Fading Channels

Guessing Random Additive Noise Decoding (GRAND) is a code-agnostic decoding technique for short-length and high-rate channel codes. GRAND tries to guess the channel noise by generating test error patterns (TEPs), and the sequence of the TEPs is the main difference between different GRAND variants. In this work, we extend the application of GRAND to multipath frequency non-selective Rayleigh fading communication channels, and we refer to this GRAND variant as Fading-GRAND. The proposed Fading-GRAND adapts its TEP generation to the fading conditions of the underlying communication channel, outperforming traditional channel code decoders in scenarios with $L$ spatial diversity branches as well as scenarios with no diversity. Numerical simulation results show that the Fading-GRAND outperforms the traditional Berlekamp-Massey (B-M) decoder for decoding BCH code $(127,106)$ and BCH code $(127,113)$ by $\mathbf{0.5\sim6.5}$ dB at a target FER of $10^{-7}$. Similarly, Fading-GRAND outperforms GRANDAB, the hard-input variation of GRAND, by $0.2\sim8$ dB at a target FER of $10^{-7}$ with CRC $(128,104)$ code and RLC $(128,104)$. Furthermore the average complexity of Fading-GRAND, at $\frac{E_b}{N_0}$ corresponding to target FER of $10^{-7}$, is $\frac{1}{2}\times\sim \frac{1}{46}\times$ the complexity of GRANDAB.

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arXiv2022

High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND

Ultra-reliable low-latency communication (URLLC), a major 5G New-Radio use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate codes. Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, Ordered Reliability Bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to $42.5$ Gbps for a code length of $128$ at a target FER of $10^{-7}$. Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRANDAB, a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least $2$ dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar $(128,105)$ code, the proposed ORBGRAND VLSI implementation has $49\times$ higher average throughput, $32\times$ times more energy efficiency, and $5\times$ more area efficiency while maintaining similar decoding performance.

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arXiv2021

High-Throughput VLSI Architecture for GRAND Markov Order

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique. Irrespective of the structure of the error correcting code, GRAND tries to guess the noise that corrupted the codeword in order to decode any linear error-correcting block code. GRAND Markov Order (GRAND-MO) is a variant of GRAND that is useful to decode error correcting code transmitted over communication channels with memory which are vulnerable to burst noise. Usually, interleavers and de-interleavers are used in communication systems to mitigate the effects of channel memory. Interleaving and de-interleaving introduce undesirable latency, which increases with channel memory. To prevent this added latency penalty, GRAND-MO can be directly used on the hard demodulated channel signals. This work reports the first GRAND-MO hardware architecture which achieves an average throughput of up to $52$ Gbps and $64$ Gbps for a code length of $128$ and $79$ respectively. Compared to the GRANDAB, hard-input variant of GRAND, the proposed architecture achieves $3$ dB gain in decoding performance for a target FER of $10^{-5}$. Similarly, comparing the GRAND-MO decoder with a decoder tailored for a $(79,64)$ BCH code showed that the proposed architecture achieves 33$\%$ higher worst case throughput and $2$ dB gain in decoding performance.

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arXiv2021

High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND technique by generating error patterns in a specific order. Moreover, their simplicity at the algorithm level renders GRAND family a desirable candidate for applications that demand very high throughput. This work reports the first-ever hardware architecture for ORBGRAND, which achieves an average throughput of up to $42.5$ Gbps for a code length of $128$ at an SNR of $10$ dB. Moreover, the proposed hardware can be used to decode any code provided the length and rate constraints. Compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar $(128,105)$ code, the proposed VLSI implementation has $49\times$ more average throughput while maintaining similar decoding performance.

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