arXiv subjects

Mary Heintz

Publications and source records attributed to Mary Heintz.

4 recordsLinked to original sources

arXiv2026

PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL

Picosecond level timing resolution is a prerequisite capability for improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. Here, we present the specification, design, and simulation results for a new Application Specific Integrated Circuit (ASIC), called PSEC6, in the TSMC 65nm process. It features 8 channels, a maximum sampling rate of 40 GSa/s, a buffer length of 204.8 nanoseconds, and a 10.24 GHz Phase Locked Loop (PLL), which is the first of its kind in the 65nm CMOS process. The event readout rate is 32 kHz, with the digitization done by an off-chip Analog-to-Digital Converter (ADC). Simulations predict a 4.0 GHz analog input bandwidth and 20 mW per channel during sampling; the 10.24 GHz PLL has a predicted jitter of 550 fs RMS at 15.7 mW. The paper describes the sampling architecture, chip signal paths, PLL design, and presents simulation results.

physics.ins-det↗

arXiv2024

Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS

1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65 nm process targetting 1 ps resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing ps time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC.

physics.ins-det↗

arXiv2016

A Brief Technical History of the Large-Area Picosecond Photodetector (LAPPD) Collaboration

The Large Area Picosecond PhotoDetector (LAPPD) Collaboration was formed in 2009 to develop large-area photodetectors capable of time resolutions measured in pico-seconds, with accompanying sub-millimeter spatial resolution. During the next three and one-half years the Collaboration developed the LAPPD design of 20 x 20 cm modules with gains greater than $10^7$ and non-uniformity less than $15\%$, time resolution less than 50 psec for single photons and spatial resolution of 700~microns in both lateral dimensions. We describe the R\&D performed to develop large-area micro-channel plate glass substrates, resistive and secondary-emitting coatings, large-area bialkali photocathodes, and RF-capable hermetic packaging. In addition, the Collaboration developed the necessary electronics for large systems capable of precise timing, built up from a custom low-power 15-GigaSample/sec waveform sampling 6-channel integrated circuit and supported by a two-level modular data acquisition system based on Field-Programmable Gate Arrays for local control, data-sparcification, and triggering. We discuss the formation, organization, and technical successes and short-comings of the Collaboration. The Collaboration ended in December 2012 with a transition from R\&D to commercialization.

physics.ins-det↗

arXiv2005

A 96-Channel FPGA-based Time-to-Digital Converter

We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA's. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 $μ$s allow deadtime-less operation in the first-level trigger. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

physics.ins-det↗