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Maryam Shojaei Baghini

Publications and source records attributed to Maryam Shojaei Baghini.

8 recordsLinked to original sources
arXiv2023

Design Analysis and Experimental Validation of Relaxation Oscillator-Based Circuit for R-C Sensors

Relaxation oscillator-based circuits are widely used for interfacing various resistive and capacitive sensors. The electrical equivalent of most resistive and capacitive sensors is represented using a parallel combination of resistor and capacitor. The relaxation oscillator-based circuits are not suitable for parallel R-C sensors. In this paper, we propose a modified circuit for parallel R-C sensors. The proposed relaxation oscillator-based circuit is based on a dual-slope and charge transfer technique to measure the resistance and capacitance of parallel R-C sensors separately. In addition, the paper provides a detailed analysis and design considerations for the oscillator design by taking into account the various sources of non-idealities. A method to reduce the error by using single-cycle averaging is also introduced. To verify the analyzed design criteria, the circuit is tested with multiple operational amplifiers with different non-idealities. Experimental results verify the performance of the proposed circuit. The circuit is tested for a range from 10 pF to 42 pF and 100 k$Ω$ to 1 M$Ω$ for parallel R-C sensors with an error of less than 1.5\%. The circuit is tested with a fabricated water-level sensor. The result confirms the efficacy of the proposed circuit.

eess.SY↗
arXiv2020

Robust stabilization of multiport networks

This paper formulates and solves the problem of robust compensation of multiport active network. This is an important engineering problem as networks designed differ in parameter values due to tolerance during manufacture from their actual realizations in chips and hardware. Parameters also undergo changes due to environmental factors. Hence, practical use of networks requires compensation which is only possible by connecting compensating network at the ports. The resulting interconnection is then required to be stable over a range of parameter values. This is called robust compensation. This paper formulates such a problem using an extension of the coprime factorization theory well known in feedback control theory to the situation of multiport network interconnection developed in \cite{msm1} and formulates the robust stabilization problem as an $H_{\infty}$ optimization problem. The port interconnection of networks does not confirm with computation of the function of the interconnected network analogous to that of the feedback interconnection using signal flow graph. Hence the well known stabilization and stability theory of feedback systems cannot be utilized for such a problem. A new formulation of stabilization theory of network interconnection was formulated and developed by the authors in \cite{msm1}. The variations of parameters of the network are used to define a worst case neighborhood of the network in terms of its coprime fractions at the nominal values of parameters. The solution of the optimization problem is then carried out by the standard procedure of converting such a problem to the Nehari optimization problem \cite{fran}. This methodology of solving the robust compensation of multiport networks using feedback control theory is believed to be novel.

eess.SY↗
arXiv2020

Maximum Lifetime Convergecast Tree in Wireless Sensor Networks

We study the problem of building a maximum lifetime data collection tree for periodic convergecast applications in wireless sensor networks. We experimentally observe that if two nodes transmit same number of data packets, the amount of energy consumption of the nodes is approximately the same even if the payload lengths of the transmitted packets are different. This is because the major energy consumption during a packet transmission arises from radio start-up and medium access control overhead. Our formulated lifetime maximization problem captures the energy expenditure due to message transmissions/ receptions in terms of the number of data packets transmitted/ received, in contrast to prior works, which consider the number of data units (amount of sensor data generated by a node) transmitted/ received. Variable transmission power levels of the radio and accounting for the sensor energy consumption are other factors that make our problem formulation different from those in prior work. We prove that this problem is NP-complete and propose an algorithm to solve it. The performance of the proposed algorithm is experimentally evaluated using Jain's fairness index as a metric by implementing it on an actual testbed consisting of 20 sensor nodes and compared with those of the widely used shortest path tree (SPT) and random data collection tree (RDCT) algorithms. The energy consumption of different nodes under the proposed algorithm are shown to be more balanced than under SPT and RDCT algorithms. Also, the performance of the proposed algorithm in large networks is studied through simulations and is compared with those of the state-of-the-art RaSMaLai algorithm, SPT, minimum spanning tree, and RDCT based data collection schemes. Our simulations show that the proposed algorithm provides a significantly higher network lifetime compared to all the other considered data collection approaches.

cs.NI↗
arXiv2020

Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits

This paper shows how the input offset of sampling flip-flops in the Alexander phase detector affects the jitter transfer from data to the recovered clock in a clock data recovery circuit. The Alexander phase detector samples the data at both the edges of the clock in order to recover the data, as well as the clock timing information. The timing information is used in a clock recovery circuit, which is basically a PLL or a DLL. Once the PLL (or DLL) is locked, the phase detector samples the data at the center of the eye as well as at the data transitions. It is shown how the offset of the sampling flip-flop that samples the data at its transitions influences the jitter transfer from data to the recovered clock. Importantly, it is shown that zero offset is not always the best case. The effect is studied for different levels of data dependent jitter. The mechanism of this phenomenon is explained and the predictions are supported with simulations. The paper also discusses a tracking circuit that keeps the offset at the minimum jitter point.

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arXiv2019

Design and Implementation of a Wireless SensorNetwork for Agricultural Applications

We present the design and implementation of a shortest path tree based, energy efficient data collection wireless sensor network to sense various parameters in an agricultural farm using in-house developed low cost sensors. Nodes follow a synchronized, periodic sleep-wake up schedule to maximize the lifetime of the network. The implemented network consists of 24 sensor nodes in a 3 acre maize farm and its performance is captured by 7 snooper nodes for different data collection intervals: 10 minutes, 1 hour and 3 hours. The almost static nature of wireless links in the farm motivated us to use the same tree for a long data collection period(3 days). The imbalance in energy consumption across nodes is observed to be very small and the network architecture uses easy-to-implement protocols to perform different network activities including handling of node failures. We present the results and analysis of extensive tests conducted on our implementation, which provide significant insights.

cs.NI↗
arXiv2018

A Novel Method of Discrete-Time Amplification using NEMS Devices

In this paper we propose a novel method of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical (NEMS) devices. The amplifier uses mechanical devices instead of traditional solid-state circuits. The proposed NEMS-based D-T amplifier provides high gain and operate on a wide dynamic range of signals, consuming only a few micro watts of power. The proposed concept is subsequently verified using Verilog-A model of the NEMS device. Modifications in the proposed amplifier to suit different specifications are also presented.

cs.ET↗
arXiv2015

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop. The picked phase is then further fine tuned by an analog voltage controlled delay to position the sampling clock at the center of the eye. A clock domain transfer circuit then transfers the sampled data to the receiver clock domain with a maximum latency of three clock cycles. The proposed synchronizer has been designed and fabricated in 130 nm UMC MM CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate of 1.3 Gbps. Further, the proposed synchronizer has been designed and simulated in TSMC 65 nm CMOS technology. Post layout simulations show that the synchronizer consumes 1.5 mW from a 1 V supply, at a data rate of 4 Gbps in this technology.

cs.AR↗