arXiv subjects

Matthew Sarsby

Publications and source records attributed to Matthew Sarsby.

7 recordsLinked to original sources

arXiv2026

Mitigating crosstalk errors for simultaneous single-qubit gates on a superconducting quantum processor

Single-qubit gates on superconducting quantum processors are typically implemented using microwave pulses applied through dedicated control lines. However, these microwave pulses may also drive other qubits due to crosstalk arising from capacitive coupling and wavefunction overlap in systems with closely spaced transition frequencies. Crosstalk and frequency crowding increase errors during simultaneous single-qubit operations relative to isolated gates, thus forming a major bottleneck for scaling superconducting quantum processors. In this work, we combine model-based qubit frequency optimization with pulse shaping to demonstrate crosstalk error mitigation in single-qubit gates on a 49-qubit superconducting quantum processor. We introduce and experimentally verify an analytical model of simultaneous single-qubit gate error caused by microwave crosstalk that depends on a given pulse shape. By employing a model-based optimization strategy of qubit frequencies, we minimize the crosstalk-induced error across the processor and achieve a mean simultaneous single-qubit gate fidelity of 99.96% for a 16-ns gate duration, approaching the mean individual gate fidelity. To further reduce the simultaneous error and required qubit frequency bandwidth on high-crosstalk qubit pairs, we introduce a crosstalk transition suppression (CTS) pulse shaping technique that minimizes the spectral energy around transitions inducing leakage and crosstalk errors. Finally, we combine CTS with model-based frequency optimization across the device and experimentally show a systematic reduction in the required qubit frequency bandwidth for high-fidelity simultaneous gates, supported by simulations of systems with up to 1000 qubits. By alleviating constraints on qubit frequency bandwidth for parallel single-qubit operations, this work represents an important step for scaling towards larger quantum processors.

quant-ph↗

arXiv2025

Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device

Achieving high-fidelity single-qubit gates, two-qubit gates, and qubit readout is critical for building scalable, error-corrected quantum computers. However, device parameters that enhance one operation often degrade the others, making simultaneous optimization challenging. Here, we demonstrate that careful tuning of qubit-coupler coupling strengths in a superconducting circuit with two transmon qubits coupled via a tunable coupler enables high-fidelity single- and two-qubit gates, without compromising readout performance. As a result, we achieve a 40h-averaged CZ gate fidelity of 99.93%, simultaneous single-qubit gate fidelities of 99.98%, and readout fidelities over 99.94% in a single device. These results are enabled by optimized coupling parameters, an efficient CZ gate calibration experiment based on our new Phased-Averaged Leakage Error Amplification (PALEA) protocol, and a readout configuration compatible with high coherence qubits. Our results demonstrate a viable path toward scaling up superconducting quantum processors while maintaining consistently high fidelities across all core operations.

quant-ph↗

arXiv2024

Technology and Performance Benchmarks of IQM's 20-Qubit Quantum Computer

Quantum computing has tremendous potential to overcome some of the fundamental limitations present in classical information processing. Yet, today's technological limitations in the quality and scaling prevent exploiting its full potential. Quantum computing based on superconducting quantum processing units (QPUs) is among the most promising approaches towards practical quantum advantage. In this article the basic technological approach of IQM Quantum Computers is described covering both the QPU and the rest of the full-stack quantum computer. In particular, the focus is on a 20-qubit quantum computer featuring the Garnet QPU and its architecture, which we will scale up to 150 qubits. We also present QPU and system-level benchmarks, including a median 2-qubit gate fidelity of 99.5% and genuinely entangling all 20 qubits in a Greenberger-Horne-Zeilinger (GHZ) state.

quant-ph↗

arXiv2024

On-Premises Superconducting Quantum Computer for Education and Research

With a growing interest in quantum technology globally, there is an increasing need for accessing relevant physical systems for education and research. In this paper we introduce a commercially available on-site quantum computer utilizing superconducting technology, offering insights into its fundamental hardware and software components. We show how this system can be used in education to teach quantum concepts and deepen understanding of quantum theory and quantum computing. It offers learning opportunities for future talent and contributes to technological progress. Additionally, we demonstrate its use in research by replicating some notable recent achievements.

quant-ph↗

arXiv2021

Coulomb blockade thermometry beyond the universal regime

The charge localization of single electrons on mesoscopic metallic islands leads to a suppression of the electrical current, known as the Coulomb blockade. When this correction is small, it enables primary electron thermometry, as it was first demonstrated by Pekola et al. (Phys. Rev. Letters, 73, 2903 [1994]). However, in the low temperature limit, random charge offsets influence the conductance and limit the universal behavior of a single metallic island. In this work, we numerically investigate the conductance of a junction array, and demonstrate the extension of the primary regime for large arrays, even when the variations in the device parameters are taken into account. We find that our simulations agree well with measured conductance traces in the submillikelvin electron temperature regime.

cond-mat.mes-hall↗

arXiv2020

500 microkelvin nanoelectronics

Fragile quantum effects such as single electron charging in quantum dots or macroscopic coherent tunneling in superconducting junctions are the basis of modern quantum technologies. These phenomena can only be observed in devices where the characteristic spacing between energy levels exceeds the thermal energy, $k_\textrm{B}T$, demanding effective refrigeration techniques for nanoscale electronic devices. Commercially available dilution refrigerators have enabled typical electron temperatures in the $10$ to $100\,$mK regime, however indirect cooling of nanodevices becomes inefficient due to stray radiofrequency heating and weak thermal coupling of electrons to the device substrate. Here we report on passing the millikelvin barrier for a nanoelectronic device. Using a combination of on-chip and off-chip nuclear refrigeration, we reach an ultimate electron temperature of $T_\textrm{e}=421\pm35\,μ$K and a hold time exceeding $85\,$hours below $700\,μ$K measured by a self-calibrated Coulomb-blockade thermometer.

cond-mat.mes-hall↗

arXiv2020

Indium as a high cooling power nuclear refrigerant for quantum nanoelectronics

The frontiers of quantum electronics have been linked to the discovery of new refrigeration methods since the discovery of superconductivity at a temperature around $4\,$K, enabled by the liquefaction of helium. Since then, the advances in cryogenics led to discoveries such as the quantum Hall effect and new technologies like superconducting and semiconductor quantum bits. Presently, nanoelectronic devices typically reach electron temperatures around $10\,$mK to $100\,$mK by commercially available dilution refrigerators. However, cooling electrons via the encompassing lattice vibrations, or phonons, becomes inefficient at low temperatures. Further progress towards lower temperatures requires new cooling methods for electrons on the nanoscale, such as direct cooling with nuclear spins, which themselves can be brought to microkelvin temperatures by adiabatic demagnetization. Here, we introduce indium as a nuclear refrigerant for nanoelectronics and demonstrate that solely on-chip cooling of electrons is possible down to $3.2\pm0.1\,$mK, limited by the heat leak via the electrical connections of the device.

cond-mat.mes-hall↗