arXiv subjects

Mauro Dossena

Publications and source records attributed to Mauro Dossena.

4 recordsLinked to original sources

arXiv2026

Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles

To ensure high electrostatic integrity in ultra-scaled field-effect transistors (FETs), thin gate dielectric layers are typically needed, potentially giving rise to (strong) leakage currents. Being able to model this effect is therefore crucial. Here, we show how gate leakage currents can be computed at the ab initio level in WS$_2$-hBN FETs by extending the well-established quantum transmitting boundary method (QTBM). Two main challenges are tackled: (i) the calculation of the open boundary conditions (OBCs) for the gate contacts and (ii) the solution of the resulting sparse linear system of equations A x = b where the matrix A possesses an unstructured sparsity pattern. We demonstrate that the proposed method outperforms the state of the art and can be readily applied to simulate transistors with gate lengths exceeding 25 nm.

cond-mat.mtrl-sci↗

arXiv2026

Ab initio Modeling of MoS2/Oxide Device Interfaces with Machine Learned Electronic Structures

We introduce a new ab initio approach to simulate semiconductor devices that integrates scalable machine-learned (ML) electronic structure models with an advanced quantum transport (QT) solver. The developed framework enables 10,000X speedups over density functional theory to produce the Hamiltonian matrix of devices made of >20,000 atoms, while offering high prediction accuracy. We use its unique features to investigate MoS2/oxide samples and single-layer MoS2 field-effect transistors, where the surrounding oxide layers, here, HfO2 or Al2O3, are explicitly included into the QT domain. In particular, we reveal that the presence of undercoordinated metal atoms (Hf or Al) close to the semiconductor-oxide interface significantly affects the magnitude of the electronic current and its propagation through MoS2.

cond-mat.mtrl-sci↗

arXiv2026

Optimizing Semiconductor Device Simulations through Low-Precision Arithmetic

Architectural changes in GPUs, especially the promotion of low-precision computational units, pose significant challenges to traditional, FP64-based high-performance computing (HPC) applications, while also presenting opportunities. Adopting reduced-precision data formats is a promising avenue to exploit the increased throughput capabilities. However, straightforward data conversions may lead to degraded accuracy or even erroneous results. For a given application, only an in-depth analysis of its numerical stability can reveal the potential of low-precision arithmetic. In this work, we consider the open-source quatrex package, a quantum transport solver capable of breaking the sustained FP64 Eflop/s barrier, to illustrate trade-offs between accuracy losses and computational speed-ups when moving from high- to low-precision formats. We use three representative benchmark structures to explore the application's numerical properties. Applying the gained insights to a larger, more realistic system, we achieve up to 51% higher throughput while maintaining accurate results, on 40% fewer HPC resources than the FP64 reference.

cs.CE↗

arXiv2025

Channel-last gate-all-around nanosheet oxide semiconductor transistors

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

cond-mat.mtrl-sci↗