arXiv subjects

Md. Aftab Baig

Publications and source records attributed to Md. Aftab Baig.

5 recordsLinked to original sources

arXiv2023

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials

This paper presents a simulation platform, namely CIMulator, for quantifying the efficacy of various synaptic devices in neuromorphic accelerators for different neural network architectures. Nonvolatile memory devices, such as resistive random-access memory, ferroelectric field-effect transistor, and volatile static random-access memory devices, can be selected as synaptic devices. A multilayer perceptron and convolutional neural networks (CNNs), such as LeNet-5, VGG-16, and a custom CNN named C4W-1, are simulated to evaluate the effects of these synaptic devices on the training and inference outcomes. The dataset used in the simulations are MNIST, CIFAR-10, and a white blood cell dataset. By applying batch normalization and appropriate optimizers in the training phase, neuromorphic systems with very low-bit-width or binary weights could achieve high pattern recognition rates that approach software-based CNN accuracy. We also introduce spiking neural networks with RRAM-based synaptic devices for the recognition of MNIST handwritten digits.

cs.NE↗

arXiv2022

Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network

This paper reports the impacts of temperature variation on the inference accuracy of pre-trained all-ferroelectric FinFET deep neural networks, along with plausible design techniques to abate these impacts. We adopted a pre-trained artificial neural network (N.N.) with 96.4% inference accuracy on the MNIST dataset as the baseline. As an aftermath of temperature change, a compact model captured the conductance drift of a programmed cell over a wide range of gate biases. We observed a significant inference accuracy degradation in the analog neural network at 233 K for an N.N. trained at 300 K. Finally, we deployed binary neural networks with "read voltage" optimization to ensure immunity of N.N. to accuracy degradation under temperature variation, maintaining an inference accuracy of 96%. Keywords: Ferroelectric memories

cs.LG↗

arXiv2022

Neuromorphic Computing with Ferroelectric FinFETs in the Presence of Temperature, Process Variation, Device Aging and Flicker Noise

This paper reports a comprehensive study on the impacts of temperature-change, process variation, flicker noise and device aging on the inference accuracy of pre-trained all-ferroelectric (FE) FinFET deep neural networks. Multiple-level-cell (MLC) operation with a novel adaptive-program-and-read algorithm with 100ns write pulse has been experimentally demonstrated in 5 nm thick hafnium zirconium oxide (HZO)-based FE-FinFET. With pre-trained neural network (NN) with 97.5% inference accuracy on MNIST dataset as baseline, device to device variation is shown to have negligible impact. Flicker noise characterization at various bias conditions depicts that drain current fluctuation is less than 0.7% with virtually no inference accuracy degradation. The conductance drift of a programmed cell, as an aftermath of temperature change, was captured by a compact model over a wide range of gate biases. Despite significant inference accuracy degradation at 233K for a NN trained at 300K, gate bias optimization for recovering the accuracy is demonstrated. Endurance above 10$^8$ cycles and extrapolated retention above 10 years are shown, which paves the way for edge device artificial intelligence with FE-FinFETs.

cs.ET↗

arXiv2021

Stochastic Variations in Nanoscale HZO based Ferroelectric finFETs: A Synergistic Approach of READ Optimization and Hybrid Precision Mixed Signal WRITE Operation to Mitigate the Implications on DNN Applications

This paper reports a synergistic approach of READ and WRITE optimization by deploying a high-precision digital computation unit along with a low-precision ferroelectric finFET (Fe-finFETs) based analog vector-matrix multiplication block for mitigating the impact of stochastic device variations in hafnium zirconium oxide (HZO) based Fe-finFETs.

physics.app-ph↗

arXiv2020

Formation of Uniform Crystal and Reduction of Electrical Variation in HfZrO$_2$ Ferroelectric Memory by Thermal Engineering

In this paper we proclaim excellent variation control in Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric films obtained by germination of large ferroelectric domain via extended duration of thermal annealing. 10nm thick Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric capacitors with TiN as bottom and top electrodes are fabricated and characterized. The duration of rapid thermal annealing (RTA) is varied to observe its effect on crystal formation and device electrical properties at 700C. The device to device variation in terms of coercive voltage and peak capacitance are reduced from 0.4V to 0.01V and from 2*$10^{-5}$nF/cm$^2$ to 4*$10^{-6}$nF/cm$^2$, respectively, by increasing the RTA duration. High resolution transmission electron micrograph clearly shows large and uniform ferroelectric domains with RTA of 180 seconds. Extended duration of RTA likely allows uniform crystal to form, which mitigates the stochasticity of the distribution of ferroelectric and paraelectric domains, and deterministic switching has been infused. This improvement paves the way for implementing Hf$_{0.5}$Zr$_{0.5}$O$_2$ based deeply scaled devices for memory and steep slope device applications.

physics.app-ph↗