arXiv subjects

Meysam Sohani Darban

Publications and source records attributed to Meysam Sohani Darban.

2 recordsLinked to original sources

arXiv2026

A High-Speed Differential Hybrid Voltage Level Shifter With Simultaneous Multi-Level Outputs

This paper presents a low-jitter hybrid voltage level shifter (HVLS) architecture for high-speed mixed-signal and digital power-amplifier applications. The proposed design employs a regenerative cross-coupled feedback network to simultaneously generate two synchronized voltage-domain outputs (e.g., the nominal supply voltage VDDL and one at twice its value, VDDH = 2VDDL). This enables direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, amongst other mixed-signal applications. A prototype HVLS circuit, together with an impedance-matching network and a pre-driver for high-speed off-chip characterization, was fabricated in a 22-nm FD-SOI process technology. The total die area, including all interface circuitry, is 477 x 462 um^2, while the active area of the HVLS core is 3.26 x 2 um^2. Measured at 12.2 GHz, the circuit dissipates 427.8 uW and achieves a measured rms jitter below 43 fs (10 Hz-500 kHz), limited by the noise floor of the measurement setup.

eess.SP↗

arXiv2026

236 μW Direct-RF PLL-Free Multi-PSK Transmitter Using Oscillator-Based Phase Synthesis

This paper presents a compact, low-power, direct RF multi-phase-shift keying (PSK) transmitter (TX) that eliminates the need for a phase-locked loop (PLL) by performing phase modulation directly within a ring oscillator. The proposed architecture exploits synchronized charge extraction at the oscillator's transition points to induce controlled phase shifts while maintaining constant amplitude and frequency. A time-domain multi-triggering technique is introduced to enable reconfigurable multi-mode modulation, supporting 16-PSK, 8-PSK, QPSK, and BPSK within a unified hardware structure. The TX circuit is fabricated in a 22-nm FD-SOI process and operates in the ISM band at 2.4 GHz. Measurement results indicate a symbol rate of 2 MSps with a maximum error vector magnitude (EVM) of 5.13% rms. The core TX occupies 23 {\times} 17.6 μm2 and consumes 236 μW, excluding the output driver, which delivers -10 dBm output power over a 60 MHz bandwidth. The proposed design achieves a favorable trade-off between power consumption, circuit complexity, and modulation flexibility, making it well-suited for low-power wireless applications.

eess.SY↗