Impacts of Decoder Latency on a Utility-Scale Quantum Computer Architecture
The speed of a fault-tolerant quantum computer depends in large part on the reaction time of its classical electronics, that is, the total time required by decoders and controllers to determine the outcome of a logical measurement and execute subsequent conditional logical operations. Despite its importance, the reaction time and its impact on the design of a logical microarchitecture of a quantum computer are not well understood. In this work, we perform a detailed system-level analysis of the classical and quantum resource requirements of a surface code based architecture. To this end, we construct a model of the reaction time in which the decoder latency is based on parallel space- and time-window decoding methods. In addition, we draw communication latencies from our envisioned quantum execution environment, which comprises a high-speed network of quantum processing units, controllers, decoders, and high-performance computing nodes. We use this model to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. We then show how the microarchitecture can be optimized with respect to the reaction time, and present full-system quantum resource estimates based on realistic hardware noise parameters for executing utility-scale quantum circuits of the Fermi-Hubbard model (2562 logical qubits and $4$$\times$$10^6$ $T$ gates) and NMR spectral prediction (241 logical qubits and $5.11$$\times$$10^{11}$ $T$ gates). We numerically determine the impact of improving reaction time on the code distance required for the core processor and on the size of the resource state factory. Moreover, we analyze how decoder speeds constrain the size of practically executable circuits, and show that state-of-the-art decoders will require a performance improvement of at least an order of magnitude to execute utility-scale quantum algorithms within days.