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Michał Kruszewski

Publications and source records attributed to Michał Kruszewski.

5 recordsLinked to original sources

HBS -- Hardware Build System: Characterizing and comparing direct-Tcl and indirect-abstract approaches for hardware build systems

Build systems become an indispensable part of the software implementation and deployment process. New programming languages are released with the build system integrated into the language tools, for example, Go, Rust, or Zig. However, in the hardware description domain, no official build systems have been released with the predominant Hardware Description Languages (HDL) such as VHDL or SystemVerilog. Moreover, hardware design projects are often multilingual. The paper characterizes and compares two common approaches for hardware build system implementations. The first one, the direct-Tcl approach, in which the build system code is executed directly by the EDA tool during the design build flow. The second one, the indirect-abstract approach, in which the build system produces a Tcl script, which is later run by a proper EDA tool. As none of the existing direct-Tcl build systems was close to the indirect-abstract build systems in terms of supported functionalities, the paper also presents a new direct-Tcl hardware build system called HBS. The implemented build system was used as a representative of direct-Tcl build systems in comparison with indirect-abstract build systems.

eess.SY

Evolution of the data aggregation concepts for STS readout in the CBM Experiment

The STS detector in the CBM experiment delivers data via multiple e-links connected to GBTX ASICs. In the process of data aggregation, that data must be received, combined into a smaller number of streams, and packed into so-called microslices containing data from specific periods. The aggregation must consider data randomization due to amplitude-dependent processing time in the FEE ASICs and different occupancy of individual e-links. During the development of the STS readout, the continued progress in the available technology affected the requirements for data aggregation, its architecture, and algorithms. The contribution presents considered solutions and discusses their properties.

physics.ins-det

SMX and front-end board tester for CBM readout chain

The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, front-end board (FEB), or a full detector module. The software written in Python may easily be integrated with higher-level testing software.

physics.ins-det

GBTX emulator for development and special versions of GBT-based readout chains

The GBTX ASIC is a standard solution for providing fast control and data readout for radiation detectors used in HEP experiments. However, it is subject to export control restrictions due to the usage of radiation-hard technology. An FPGA-based GBTX emulator (GBTxEMU) has been developed to enable the development of GBT-based readout chains in countries where the original GBTX cannot be imported. Thanks to utilizing a slightly modified GBT-FGPA core, it maintains basic compatibility with standard GBT-based systems. The GBTxEMU also may be an interesting solution for developing GBT-based readout chains for less demanding experiments.

physics.ins-det

Easy and structured approach for software and firmware co-simulation for bus centric designs

Although software and firmware co-simulation is gaining popularity, it is still not widely used in the FPGA designs. This work presents easy and structured approach for software and firmware co-simulation for bus centric designs. The proposed approach is very modular and software language agnostic. The only requirement is that the firmware design is accessible via some kind of system bus. The concept has been used for testing DAQ system being developed for high energy physics experiment.

cs.OH