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Michael Hush

Publications and source records attributed to Michael Hush.

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Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting

Quantum computer hardware is predicted to scale over hundreds of thousands of qubits coming online in the next decade. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of $1,000$ logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551x reduction in algorithmic logical error and up to 138x reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 days, which can be reduced to 4.9 days via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 days. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.

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Achieving computational gains with quantum error-correction primitives: Generation of long-range entanglement enhanced by error detection

The resource overhead required to achieve net computational benefits from quantum error correction (QEC) limits its utility while current systems remain constrained in size, despite exceptional progress in experimental demonstrations. In this paper, we demonstrate that the strategic application of QEC primitives without logical encoding can yield significant advantages on superconducting processors--relative to any alternative error-reduction strategy--while only requiring a modest overhead. We first present a novel protocol for implementing long-range CNOT gates that relies on a unitarily prepared Greenberger-Horne-Zeilinger (GHZ) state as well as a unitary disentangling step; the protocol natively introduces an error-detection process using the disentangled qubits as flags. We demonstrate that it achieves state-of-the-art gate fidelities of over 85% across up to 40 lattice sites, significantly and consistently outperforming the best alternative measurement-based protocol without introducing any additional ancilla qubits. We then apply sparse stabilizer measurements to generate large GHZ states by detecting bit-flip and amplitude-damping errors. Employing this technique in combination with deterministic error suppression, we generate a 75-qubit GHZ state exhibiting genuine multipartite entanglement, the largest reported to date. The generation requires no more than 9 ancilla qubits and the fraction of samples discarded due to errors grows no higher than 78%, far lower than previous discard fractions required for tests using comparable numbers of fully encoded qubits. This work in total represents compelling evidence that adopting QEC primitives on current-generation devices can deliver substantial net benefits.

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Integrated error-suppressed pipeline for quantum optimization of nontrivial binary combinatorial optimization problems on gate-model hardware at the 156-qubit scale

We introduce a novel hybrid quantum-classical variational optimization method for unconstrained binary combinatorial optimization problems on gate-model quantum computers, integrating a custom variational ansatz, staged feedback-based dual variational parameter update strategies, efficient parametric compilation, automated error suppression during hardware execution, and scalable O($n$) classical post-processing to correct for bitflip errors. Without this integrated approach, we show that standard circuit execution at scale produces output indistinguishable from random sampling, establishing the necessity of each pipeline component. We benchmark the method on IBM superconducting quantum computers for classically nontrivial optimization problems, where the optimization is conducted on hardware with no use of classical simulation or prior knowledge of the solution. For Max-Cut on random regular graphs with topologies not matched to device connectivity, the method achieves approximation ratios of 100% for unweighted 3-regular graphs up to 156 nodes, weighted regular graphs up to 80 nodes, and weighted 7-regular graphs up 50 nodes. Applied to higher-order binary optimization, the method finds the ground state energy of 127- and 156-qubit spin-glass models matched to device topology with linear, quadratic, and cubic interaction terms, achieving approximation ratios of at least 99.5% across all instances tested. The method consistently outperforms a classical local solver across all problems. Where published results on identical problem instances are available, our method demonstrates competitive or superior performance. These results demonstrate that an appropriately engineered approach enables gate-model quantum computers to produce high-quality solutions for nontrivial binary optimization problems at the 156 qubit scale, where naive implementations are insufficient for good performance.

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Learning to rank quantum circuits for hardware-optimized performance enhancement

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit ibmq_guadalupe device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

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Experimental benchmarking of an automated deterministic error suppression workflow for quantum algorithms

Excitement about the promise of quantum computers is tempered by the reality that the hardware remains exceptionally fragile and error-prone, forming a bottleneck in the development of novel applications. In this manuscript, we describe and experimentally test a fully autonomous workflow designed to deterministically suppress errors in quantum algorithms from the gate level through to circuit execution and measurement. We introduce the key elements of this workflow, delivered as a software package called Fire Opal, and survey the underlying physical concepts: error-aware compilation, automated system-wide gate optimization, automated dynamical decoupling embedding for circuit-level error cancellation, and calibration-efficient measurement-error mitigation. We then present a comprehensive suite of performance benchmarks executed on IBM hardware, demonstrating up to > 1000X improvement over the best alternative expert-configured techniques available in the open literature. Benchmarking includes experiments using up to 16 qubit systems executing: Bernstein Vazirani, Quantum Fourier Transform, Grover's Search, QAOA, VQE, Syndrome extraction on a five-qubit Quantum Error Correction code, and Quantum Volume. Experiments reveal a strong contribution of Non-Markovian errors to baseline algorithmic performance; in all cases the deterministic error-suppression workflow delivers the highest performance and approaches incoherent error bounds without the need for any additional sampling or randomization overhead, while maintaining compatibility with all additional probabilistic error suppression techniques.

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Experimental Deep Reinforcement Learning for Error-Robust Gateset Design on a Superconducting Quantum Computer

Quantum computers promise tremendous impact across applications -- and have shown great strides in hardware engineering -- but remain notoriously error prone. Careful design of low-level controls has been shown to compensate for the processes which induce hardware errors, leveraging techniques from optimal and robust control. However, these techniques rely heavily on the availability of highly accurate and detailed physical models which generally only achieve sufficient representative fidelity for the most simple operations and generic noise modes. In this work, we use deep reinforcement learning to design a universal set of error-robust quantum logic gates on a superconducting quantum computer, without requiring knowledge of a specific Hamiltonian model of the system, its controls, or its underlying error processes. We experimentally demonstrate that a fully autonomous deep reinforcement learning agent can design single qubit gates up to $3\times$ faster than default DRAG operations without additional leakage error, and exhibiting robustness against calibration drifts over weeks. We then show that $ZX(-\pi/2)$ operations implemented using the cross-resonance interaction can outperform hardware default gates by over $2\times$ and equivalently exhibit superior calibration-free performance up to 25 days post optimization using various metrics. We benchmark the performance of deep reinforcement learning derived gates against other black box optimization techniques, showing that deep reinforcement learning can achieve comparable or marginally superior performance, even with limited hardware access.

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Software tools for quantum control: Improving quantum computer performance through noise and error suppression

Manipulating quantum computing hardware in the presence of imperfect devices and control systems is a central challenge in realizing useful quantum computers. Susceptibility to noise limits the performance and capabilities of noisy intermediate-scale quantum (NISQ) devices, as well as any future quantum computing technologies. Fortunately quantum control enables efficient execution of quantum logic operations and algorithms with built-in robustness to errors, without the need for complex logical encoding. In this manuscript we introduce software tools for the application and integration of quantum control in quantum computing research, serving the needs of hardware R&D teams, algorithm developers, and end users. We provide an overview of a set of python-based classical software tools for creating and deploying optimized quantum control solutions at various layers of the quantum computing software stack. We describe a software architecture leveraging both high-performance distributed cloud computation and local custom integration into hardware systems, and explain how key functionality is integrable with other software packages and quantum programming languages. Our presentation includes a detailed mathematical overview of central product features including a flexible optimization toolkit, filter functions for analyzing noise susceptibility in high-dimensional Hilbert spaces, and new approaches to noise and hardware characterization. Pseudocode is presented in order to elucidate common programming workflows for these tasks, and performance benchmarking is reported for numerically intensive tasks, highlighting the benefits of the selected cloud-compute architecture. Finally, we present a series of case studies demonstrating the application of quantum control solutions using these tools in real experimental settings for both trapped-ion and superconducting quantum computer hardware.

quant-ph

Qiskit Backend Specifications for OpenQASM and OpenPulse Experiments

As interest in quantum computing grows, there is a pressing need for standardized API's so that algorithm designers, circuit designers, and physicists can be provided a common reference frame for designing, executing, and optimizing experiments. There is also a need for a language specification that goes beyond gates and allows users to specify the time dynamics of a quantum experiment and recover the time dynamics of the output. In this document we provide a specification for a common interface to backends (simulators and experiments) and a standarized data structure (Qobj --- quantum object) for sending experiments to those backends via Qiskit. We also introduce OpenPulse, a language for specifying pulse level control (i.e. control of the continuous time dynamics) of a general quantum device independent of the specific hardware implementation.

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