arXiv subjects

Miguel Peón-Quirós

Publications and source records attributed to Miguel Peón-Quirós.

10 recordsLinked to original sources

arXiv2026

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

The growing demand for on-device AI necessitates energy-efficient execution of DNN based applications on resource-constrained ultra-low power (ULP) platforms. Heterogeneous architectures, combining specialized processing elements (PEs), have emerged as a key solution for achieving the required performance and energy efficiency. However, optimizing energy while executing applications on these platforms requires efficiently managing platform resources like PEs, power features, and memory footprint, all while adhering to critical application deadlines. This paper presents MEDEA, a novel design-time multi-objective manager for energy-efficient DNN inference on Heterogeneous ULP (HULP) platforms. MEDEA uniquely integrates: kernel-level dynamic voltage and frequency scaling (DVFS) for dynamic energy adaptation; kernel-level granularity scheduling, suitable for specialized accelerators; memory-aware adaptive tiling to navigate severe memory constraints; and all within a timing constraint-based optimization strategy, which minimizes energy based on application deadline. To showcase practical viability, we evaluate MEDEA on HEEPtimize, a heterogeneous ULP platform (22 nm, FPGA-prototyped) featuring a RISC-V processor besides Near-Memory Computing (NMC) and Coarse-Grained Reconfigurable Array (CGRA) accelerators. Experimental results, using a biomedical seizure detection case study, demonstrate that MEDEA achieves overall energy reductions of up to 38% compared to representative state-of-the-art methods, while consistently meeting all timing and memory requirements. This effectiveness is attributed to its integrated features, with our analysis showing that kernel-level DVFS alone can be responsible for over 31% of the energy savings in specific scenarios.

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arXiv2026

Evaluating Architectural Trade-offs in CGRAs: The Impact of Scratchpad Memory and Heterogeneity on Compute-Intensive Kernels

Modern edge computing applications, particularly high-throughput stream processing like Vision Transformers (ViTs), demand massive spatial parallelism and efficient data movement under tight power and area constraints. Coarse-Grained Reconfigurable Architectures (CGRAs) offer a promising paradigm to balance performance, flexibility, and energy efficiency. This paper analyzes the impact of two critical CGRA design choices: processing element heterogeneity and local data reuse support. We evaluate essential computational kernels (Fast Fourier Transform (FFT) and General Matrix Multiply (GEMM)) alongside an end-to-end seizure detection transformer workload across two distinct configurations: a baseline homogeneous architecture and a heterogeneous evolution integrating specialized functional units with an Scratchpad Memory (SPM). Our evaluation demonstrates that the SPM significantly optimizes data movement, reducing memory traffic eightfold compared to a memory-less design. While the heterogeneous architecture achieves superior energy efficiency for data-shuffling tasks, the homogeneous design minimizes area overhead by 4.4x to 8.2x relative to state-of-the-art CGRAs. Furthermore, it sustains a 700 MHz operating frequency, enabling up to a 5x execution speedup over the heterogeneous configuration during matrix computations. Ultimately, this work provides an architectural roadmap for selecting CGRA fabrics based on the arithmetic intensity, performance goals, and resource envelopes of edge-scale workloads.

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arXiv2026

astroCAMP: A Community Benchmark and Co-Design Framework for Sustainable SKA-Scale Radio Imaging

The Square Kilometre Array (SKA) will operate one of the world's largest continuous scientific data systems, sustaining petascale imaging under strict power envelopes. Current radio-interferometric pipelines typically achieve only 4-14% of hardware peak utilization due to memory and I/O bottlenecks, incurring high energy, operational, and carbon costs, further compounded by the absence of standardised cross-layer metrics and fidelity tolerances for principled hardware--software co-design. We present astroCAMP, a reproducible benchmarking and co-design framework for SKA-scale imaging, contributing: (1) a unified metric suite spanning performance, utilisation, memory/data-movement, sustainability, economics, and scientific fidelity; (2) standardised SKA-representative datasets and benchmark configurations for reproducible cross-platform evaluation; (3) a multi-objective co-design formulation linking quality constraints to time-, energy-, carbon-, and cost-to-solution; and (4) a design-space exploration workflow to derive Pareto-optimal operating regions. We evaluate WSClean+IDG on an AMD EPYC 9334 CPU and NVIDIA H100 GPU, revealing orchestration and synchronization bottlenecks despite efficient kernels, limited CPU strong scaling, and location-dependent carbon/cost efficiency. We illustrate astroCAMP for heterogeneous CPU--FPGA exploration and call on the SKA community to define quantifiable fidelity thresholds to accelerate principled optimisation for SKA-scale imaging.

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arXiv2026

GeneTEK: Low-power, high-performance and scalable FPGA architecture for exact unit-cost edit distance

The advent of next-generation sequencing (NGS) has revolutionized genomic research by enabling cost-effective, high-throughput sequencing of a diverse range of organisms. This breakthrough has unleashed a "Cambrian explosion" in genomic data volume and diversity. This volume of workloads places genomics among the top four big data challenges anticipated for this decade. In this context, pairwise sequence alignment represents a very time- and energy-intensive step in common bioinformatics pipelines. Speeding up this step requires the implementation of heuristic approaches, optimized algorithms, and/or hardware acceleration. Although state-of-the-art CPU and GPU implementations have demonstrated significant performance gains, recent FPGA implementations have shown improved energy efficiency. However, the latter often suffer from limited read-length scalability due to constraints on hardware resources when aligning longer sequences. In this work, we present a flexible FPGA-based accelerator template scalable up to 1000 bp that implements Myers's algorithm to compute exact unit-cost edit-distance using high-level synthesis and a worker-based architecture. GeneTEK, a set of instances of this accelerator template in a Xilinx Zynq UltraScale+ FPGA, achieves up to 113% increase in execution speed and up to 111x reduction in energy consumption compared to leading CPU and GPU solutions, while fitting comparison matrices up to 13x larger than previous FPGA-based systolic-array solutions. By following a SW-HW co-design approach, GeneTEK exploits parallelization at multiple levels and efficient memory use to deliver a scalable and accurate FPGA-based accelerator. These results reaffirm the potential of FPGAs as an energy-efficient platform for pairwise alignment of read-lengths up to 1000 bp.

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arXiv2025

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications

In this work, we present X-HEEP, an open-source, configurable, and extendible RISC-V platform for ultra-low-power edge applications (TinyAI). X-HEEP features the eXtendible Accelerator InterFace (XAIF), which enables seamless integration of accelerators with varying requirements along with an extensive internal configuration of cores, memory, bus, and peripherals. Moreover, it supports various development flows, including FPGA prototyping, ASIC implementation, and mixed SystemC-RTL modeling, enabling efficient exploration and optimization. Implemented in TSMC's 65 nm CMOS technology (300 MHz, 0.8 V), X-HEEP achieves a minimal footprint of only 0.15 mm2 and consumes just 29 uW of leakage power. As a demonstrator of the configurability and low overhead of X-HEEP as a host platform, we present a study integrating it with near-memory accelerators targeting early-exit dynamic network applications, achieving up to 7.3 x performance speedup and 3.6 x energy improvement on the resulting heterogeneous system compared to CPU-only execution.

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arXiv2025

Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems

In this paper, we present the new FPGA EMUlation (FEMU), an open-source and configurable emulation framework for prototyping and evaluating TinyAI heterogeneous systems (HS). FEMU leverages the capability of system-on-chip (SoC)-based FPGAs to combine the under-development HS implemented in a reconfigurable hardware region (RH) for quick prototyping with a software environment running under a standard operating system in a control software region (CS) for supervision and communication. To evaluate our approach, we built the X-HEEP FPGA EMUlation (X-HEEP-FEMU) platform by instantiating the proposed framework with real-world hardware and software components. X-HEEP-FEMU is deployed on the Xilinx Zynq-7020 SoC and integrates the eXtendible Heterogeneous Energy Efficient Platform (X-HEEP) host in the RH, a Linux-based Python environment on the ARM Cortex-A9 CS, and energy models derived from a TSMC 65 nm CMOS silicon implementation of X-HEEP, called HEEPocrates.

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arXiv2025

CEO-DC: Driving Decarbonization in HPC Data Centers with Actionable Insights

The rapid growth of data centers is increasing energy demand and widening the carbon gap in the ICT sector, as fossil fuels still dominate global energy production. Addressing this challenge requires collaboration across research, policy, and industry to rethink how computing infrastructures are designed and scaled sustainably. This work addresses central trade-offs in procurement decisions that affect carbon emissions, economic costs, and scaling of compute resources. We present these factors in a holistic decision-making framework for Carbon and Economy Optimization in Data Centers (CEO-DC). CEO-DC introduces new carbon and price metrics that enable DC managers, platform designers, and policymakers to make informed decisions. Applying CEO-DC to current trends in AI and HPC reveals that, in 72% of the cases, platform improvements lag behind demand growth. Moreover, prioritizing energy efficiency over latency can reduce the economic appeal of sustainable designs. Our analysis shows that in many countries with electricity with medium to high carbon intensity, replacing platforms older than four years could reduce their projected emissions by at least 75%. However, current carbon incentives worldwide remain insufficient to steer data center procurement strategies toward sustainable goals. In summary, our findings underscore the need for a shift in hardware design and faster grid decarbonization to ensure sustainability and technological viability.

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arXiv2024

Enabling Efficient Wearables: An Analysis of Low-Power Microcontrollers for Biomedical Applications

Breakthroughs in ultra-low-power chip technology are transforming biomedical wearables, making it possible to monitor patients in real time with devices operating on mere μW. Although many studies have examined the power performance of commercial microcontrollers, it remains unclear which ones perform best across diverse application profiles and which hardware features are most crucial for minimizing energy consumption under varying computational loads. Identifying these features for typical wearable applications and understanding their effects on performance and energy efficiency are essential for optimizing deployment strategies and informing future hardware designs. In this work, we conduct an in-depth study of state-of-the-art (SoA) micro-controller units(MCUs) in terms of processing capability and energy efficiency using representative end-to-end SoA wearable applications. We systematically benchmark each platform across three primary application phases: idle, data acquisition, and processing, allowing a holistic assessment of the platform processing capability and overall energy efficiency across varying patient-monitoring application profiles. Our detailed analysis of performance and energy discrepancies across different platforms reveals key strengths and limitations of the current low-power hardware design and pinpoints the strengths and weaknesses of SoA MCUs. We conclude with actionable insights for wearable application designers and hardware engineers, aiming to inform future hardware design improvements and support optimal platform selection for energy-constrained biomedical applications.

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arXiv2024

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators

The field of edge computing has witnessed remarkable growth owing to the increasing demand for real-time processing of data in applications. However, challenges persist due to limitations in performance and power consumption. To overcome these challenges, heterogeneous architectures have emerged that combine host processors with specialized accelerators tailored to specific applications, leading to improved performance and reduced power consumption. However, most of the existing platforms lack the necessary configurability and extendability options for integrating custom accelerators. To overcome these limitations, we introduce in this paper the eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP). X-HEEP is an open-source platform designed to natively support the integration of ultra-low-power edge accelerators. It provides customization options to match specific application requirements by exploring various core types, bus topologies, addressing modes, memory sizes, and peripherals. Moreover, the platform prioritizes energy efficiency by implementing low-power strategies, such as clock-gating and power-gating. We demonstrate the real-world applicability of X-HEEP by providing an integration example tailored for healthcare applications that includes a coarse-grained reconfigurable array (CGRA) and in-memory computing (IMC) accelerators. The resulting design, called HEEPocrates, has been implemented both in field programmable gate array (FPGA) on the Xilinx Zynq-7020 chip and in silicon with TSMC 65nm low-power CMOS technology. We run a set of healthcare applications and measure their energy consumption to demonstrate the alignment of our chip with other state-of-the-art microcontrollers commonly adopted in this domain. Moreover, we present the energy benefits of 4.9x and 4.8x gained by exploiting the integrated CGRA and IMC accelerators compared to running on the host CPU.

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arXiv2022

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, they are inflexible when facing application-wide optimizations or functionality upgrades. Conversely, programmable cores offer higher flexibility, but often with a penalty in area, performance, and, above all, energy consumption. In this paper, we propose VWR2A, an architecture that integrates high computational density and low power memory structures (i.e., very-wide registers and scratchpad memories). VWR2A narrows the energy gap with similar or better performance on FFT kernels with respect to an FFT accelerator. Moreover, VWR2A flexibility allows to accelerate multiple kernels, resulting in significant energy savings at the application level.

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