Mihai Timis | Searcharxiv

arXiv2009

Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal

In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostable system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used an external clock signal, CK.

cs.OH↗

arXiv2009

Output Width Signal Control In Asynchronous Digital Systems Using Monostable Circuits

In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostable system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used a monostable circuit.

cs.OH↗

arXiv2009

Design of Log-Map / Max-Log-Map Decoder

The process of turbo-code decoding starts with the formation of a posteriori probabilities (APPs) for each data bit, which is followed by choosing the data-bit value that corresponds to the maximum a posteriori (MAP) probability for that data bit. Upon reception of a corrupted code-bit sequence, the process of decision making with APPs allows the MAP algorithm to determine the most likely information bit to have been transmitted at each bit time.

cs.IT↗