arXiv subjects

Mikaël Cassé

Publications and source records attributed to Mikaël Cassé.

4 recordsLinked to original sources

arXiv2026

Band Tail States: Speed Bump or End of the Road for Two-Dimensional Semiconductors?

We propose that the path to realizing the full potential of two-dimensional (2D) electronics lies in understanding and mastering their energy band tail states (BTS). Unlike silicon, which benefits from sharp band edges (Urbach energy $E_\rm U$ ~ 10 meV), today's monolayer 2D semiconductors have rough band edges ($E_\rm U$ ~ 100 meV) caused by spatial potential inhomogeneity. Comparing a physics-based electrical model to experiments, we demonstrate that BTS cause reduced effective mobility and "slow" transistor turn-on with excessive gate voltage in monolayer 2D transistors, which sets a fundamental limit for their energy-efficient operation. We also show that BTS effects in 2D transistors could be mitigated with higher gate capacitance, with strain engineering, and by using bilayer instead of monolayer 2D channels, as long as $E_\rm U$ is reduced below ~ 50 meV. This work provides a theoretical framework and design guidelines to navigate these fundamental limits, and to enable successful integration of 2D semiconductors into low-power nanoelectronics.

cond-mat.mtrl-sci↗

arXiv2026

Origins of microwave losses in superconducting circuits made with silicon-on-insulator substrates

Silicon-on-insulator technology is widely used to fabricate silicon based devices, from advanced transistors to photonic circuits or nanomechanical systems. Integrating low loss superconducting quantum circuits with silicon-on-insulator substrates enables to couple the advantages offered by the mature silicon technology to the exquisite sensitivity of superconducting circuits. The natural approach, inherited from research in superconducting microwave devices, is to use a substrate made with highly resistive silicon, known for its low level of microwave losses. In this work, using superconducting microwave resonators, we show that counterintuitively, standard resistivity silicon-on-insulator substrates perform better than high resistivity silicon-on-insulator substrates at cryogenic temperatures. In the latter case, the presence of a parasitic sheet conduction at the interface between bulk silicon and silicon oxide acts as the dominant loss mechanism. This parasitic sheet can be suppressed using substrates with intentionally induced traps. In such substrates, losses are ultimately limited by the dielectric losses of the silicon oxide layer. These substrates offer interesting perspectives for the development of superconducting nanoelectromechanical systems. First, the release, i.e. the removal of the silicon oxide, could be limited to the moving parts, thereby maintaining the mechanical integrity of the rest of the device. Additionally, such structure would enhance heat evacuation into the bulk of the substrate which is an issue in current devices such as microwave-to-optics converters.

cond-mat.mes-hall↗

arXiv2025

Transport characterization and quantum dot coupling in commercial 22FDX

Different groups worldwide have been working with the GlobalFoundries 22nm platform (22FDX) with the hopes of industrializing the fabrication of Si spin qubits. To guide this effort, we have performed a systematic study of six of the foundry's processes of reference (POR). Using effective mobility as a figure of merit, we study the impact of gate stack, channel type and back bias as a function of temperature. This screening process selected qubit devices that allowed us to couple quantum dots along both the length and width of the Si channel. We present stability diagrams with clear and regular honeycomb patterns, where spurious elements such as dopants are not observed. By combining these results with room and low temperature simulations, we provide insights into potential technology optimizations and show both the utility of qubit pre-screening protocols as well as the advantages of leveraging forward body bias within an FDSOI (Fully Depleted Silicon-On-Insulator) qubit platform.

cond-mat.mes-hall↗

arXiv2016

Contact resistances in trigate and FinFET devices in a Non-Equilibrium Green's Functions approach

We compute the contact resistances $R_{\rm c}$ in trigate and FinFET devices with widths and heights in the 4 to 24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness and Coulomb scattering are taken into account. We show that $R_{\rm c}$ represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of $R_{\rm c}$, and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below $\simeq 50$ nm$^2$. We also highlight the role of the charges trapped at the interface between silicon and the spacer material.

cond-mat.mes-hall↗