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Mohammad Salehi Fashami

Publications and source records attributed to Mohammad Salehi Fashami.

9 recordsLinked to original sources

Energy-efficient switching of nanomagnets for computing: Straintronics and other methodologies

The need for increasingly powerful computing hardware has spawned many ideas stipulating, primarily, the replacement of traditional transistors with alternate "switches" that dissipate miniscule amounts of energy when they switch and provide additional functionality that are beneficial for information processing. An interesting idea that has emerged recently is the notion of using two-phase (piezoelectric/magnetostrictive) multiferroic nanomagnets with bistable (or multi-stable) magnetization states to encode digital information (bits), and switching the magnetization between these states with small voltages (that strain the nanomagnets) to carry out digital information processing. The switching delay is ~1 ns and the energy dissipated in the switching operation can be few to tens of aJ, which is comparable to, or smaller than, the energy dissipated in switching a modern-day transistor. Unlike a transistor, a nanomagnet is "non-volatile", so a nanomagnetic processing unit can store the result of a computation locally without refresh cycles, thereby allowing it to double as both logic and memory. These dual-role elements promise new, robust, energy-efficient, high-speed computing and signal processing architectures (usually non-Boolean and often non-von-Neumann) that can be more powerful, architecturally superior (fewer circuit elements needed to implement a given function) and sometimes faster than their traditional transistor-based counterparts. This topical review covers the important advances in computing and information processing with nanomagnets with emphasis on strain-switched multiferroic nanomagnets acting as non-volatile and energy-efficient switches - a field known as "straintronics". It also outlines key challenges in straintronics.

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Exploring Performance, Coherence, and Clocking of Magnetization in Multiferroic Four-State Nanomagnets

Nanomagnetic memory and logic are currently seen as promising candidates to replace current digital computing architectures due to its superior energy-efficiency, non-volatility and propensity for highly dense and low-power applications. In this work, we investigate the use of shape engineering (concave and diamond shape) to introduce biaxial anisotropy in single domain nanomagnets, giving rise to multiple easy and hard axes. Such nanomagnets, with dimensions of 100 nm x 100 nm, double the logic density of conventional two-state nanomagnetic devices by encoding more information (four binary bits:00,11,10,01) per nanomagnet and can be used in memory and logic devices as well as in higher order information processing applications. We study reliability, magnetization switching coherence, and show, for the first time, the use of voltage-induced strain for the clocking of magnetization in these four-state nanomagnets. Critical parameters such as size, thickness, concavity, and geometry of two types of four-state nanomagnets are also investigated. This analytical study provides important insights into achieving reliable and coherent single domain nanomagnets and low-energy magnetization clocking in four-state nanomagnets, paving the way for potential applications in advanced technologies.

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Switching of Dipole Coupled Multiferroic Nanomagnets in the Presence of Thermal Noise: Reliability of Nanomagnetic Logic

The stress-induced switching behavior of a multiferroic nanomagnet, dipole coupled to a hard nanomagnet, is numerically studied by solving the stochastic Landau-Lifshitz-Gilbert (LLG) equation for a single domain macro-spin state. Different factors were found to affect the switching probability in the presence of thermal noise at room temperature: (i) dipole coupling strength, (ii) stress levels, and (iii) stress withdrawal rates (ramp rates). We report that the thermal broadening of the magnetization distribution causes large switching error rates. This could render nanomagnetic logic schemes that rely on dipole coupling to perform Boolean logic operations impractical whether they are clocked by stress or field or other means.

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Experimental Clocking of Nanomagnets with Strain for Ultra Low Power Boolean Logic

Nanomagnetic implementations of Boolean logic [1,2] have garnered attention because of their non-volatility and the potential for unprecedented energy-efficiency. Unfortunately, the large dissipative losses that take place when nanomagnets are switched with a magnetic field [3], or spin-transfer-torque [4] inhibit the promised energy-efficiency. Recently, there have been experimental reports of utilizing the Spin Hall effect for switching magnets [5-7], and theoretical proposals for strain induced switching of single-domain magnetostrictive nanomagnets [8-12], that might reduce the dissipative losses significantly. Here, we demonstrate, for the first time, that strain-induced switching of single-domain magnetostrictive nanomagnets of lateral dimensions ~200 nm fabricated on a piezoelectric substrate can implement a nanomagnetic Boolean NOT gate and unidirectional bit information propagation in dipole-coupled nanomagnets chains. This portends ultra-low-energy logic processors and mobile electronics that may be able to operate solely by harvesting energy from the environment without ever requiring a battery.

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Self-similar Magneto-electric Nanocircuit Technology for Probabilistic Inference Engines

Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in CMOS implementations. In this paper, we present a magneto-electric probabilistic technology framework for implementing probabilistic reasoning functions. The technology leverages Straintronic Magneto-Tunneling Junction (S-MTJ) devices in a novel mixed-signal circuit framework for direct computations on probabilities while enabling in-memory computations with persistence. Initial evaluations of the Bayesian likelihood estimation operation occurring during Bayesian Network inference indicate up to 127x lower area, 214x lower active power, and 70x lower latency compared to an equivalent 45nm CMOS Boolean implementation.

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Reducing error rates in straintronic multiferroic dipole-coupled nanomagnetic logic by pulse shaping

Dipole-coupled nanomagnetic logic (NML), where nanomagnets with bistable magnetization states act as binary switches and information is transferred between them via dipole coupling and Bennett clocking, is a potential replacement for conventional transistor logic since magnets dissipate less energy than transistors when they switch in response to the clock. However, dipole-coupled NML is much more error-prone than transistor logic because thermal noise can easily disrupt magnetization dynamics. Here, we study a particularly energy-efficient version of dipole-coupled NML known as straintronic multiferroic logic (SML) where magnets are clocked/switched with electrically generated mechanical strain. By appropriately shaping the voltage pulse that generates strain, the error rate in SML can be reduced to tolerable limits. In this paper, we describe the error probabilities associated with various stress pulse shapes and discuss the trade-off between error rate and switching speed in SML.

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Energy dissipation and error probability in fault-tolerant binary switching

The potential energy profile of a binary switch is a symmetric double well. Switching between the wells without energy dissipation requires time-modulating the potential barrier separating them and tilting the profile towards the desired well at the precise juncture when the barrier disappears. This demands perfect timing synchronization and is therefore fault-intolerant, even in the absence of noise. A fault-tolerant strategy that requires no time modulation of the barrier (and hence no timing synchronization) switches by tilting the profile by an amount at least equal to the barrier height and dissipates at least that amount of energy. Here, we present a third strategy that requires a time modulated barrier but no timing synchronization. It is therefore fault-tolerant in the absence of thermal noise and yet it dissipates arbitrarily small energy since an arbitrarily small tilt is required for slow and adiabatic switching. This case is exemplified with stress induced switching of a shape-anisotropic single-domain nanomagnet dipole coupled to a neighbor. We also show by examining various energy profiles and the corresponding probability distributions that when thermal noise is present, the minimum energy dissipated to switch in this scheme is 2kTln(1/p) [p = switching error probability].

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Magnetization Dynamics, Throughput and Energy Dissipation in a Universal Multiferroic Nanomagnetic Logic Gate with Fan-in and Fan-out

The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau-Lifshitz-Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled 2-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ~50 mV applied to the piezoelectric layer generating 10 MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ~ 0.5 GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2 ns with a latency of 4 ns. The total (internal + external) energy dissipated for a single gate operation at this throughput rate is found to be only ~ 1000 kT in the gate and ~3000 kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively 3 and 5 orders of magnitude more energy-efficient than complementary-metal-oxide-semiconductor-transistor (CMOS) based and spin-transfer-torque-driven nanomagnet based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be 3 orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing. Keywords: Nanomagnetic logic, multiferroics, straintronics and spintronics, Landau-Lifshitz-Gilbert equation.

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Magnetization Dynamics, Bennett Clocking and Associated Energy Dissipation in Multiferroic Logic

It has been recently shown that multiferroic logic - where logic bits are encoded in the magnetization orientation of a nanoscale magnetostrictive layer elastically coupled to a piezoelectric layer - can be Bennett clocked with small electrostatic potentials of few tens of mV applied to the piezoelectric layer. The potential generates stress in the magnetostrictive layer and rotates its magnetization by a large angle to carry out Bennett clocking. This method of clocking is far more energy-efficient than using spin transfer torque. In order to assess if such a clocking scheme can be also reasonably fast, we have studied the magnetization dynamics of a multiferroic logic array with nearest neighbor dipole coupling using the Landau-Lifshitz-Gilbert (LLG) equation. We find that switching delays of ~ 3 ns (clock rates of 0.33 GHz) can be achieved with proper design provided we clock non-adiabatically and dissipate ~48,000 kT (at room temperature) of energy per clock cycle per bit flip in the clocking circuit. This dissipation far exceeds the energy barrier separating the two logic states, which we assumed to be 32 kT to yield a bit error probability of . Had we used spin transfer torque to switch with the same ~ 3 ns delay, the energy dissipation would have been much larger (~ $6 \times 106$ kT). This shows that spin transfer torque, widely used in magnetic random access memory, is an inefficient way to switch a magnet, and multiferroic logic clocked with voltage-induced stress is a superior nanomagnetic logic scheme.

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