arXiv subjects

Mohana Rajpalke

Publications and source records attributed to Mohana Rajpalke.

3 recordsLinked to original sources

arXiv2025

Response to recent comments on Phys. Rev. B 107, 245423 (2023) and Subsection S4.3 of the Supp. Info. for Nature 638, 651-655 (2025)

The topological gap protocol (TGP) is a statistical test designed to identify a topological phase with high confidence and without human bias. It is used to determine a promising parameter regime for operating topological qubits. The protocol's key metric is the probability of incorrectly identifying a trivial region as topological, referred to as the false discovery rate (FDR). Two recent manuscripts [arXiv:2502.19560, arXiv:2503.08944] engage with the topological gap protocol and its use in Phys. Rev. B 107, 245423 (2023) and Subsection S4.3 of the Supplementary Information for Nature 638, 651-655 (2025), although they do not explicitly dispute the main results of either one. We demonstrate that the objections in arXiv:2502.19560 and arXiv:2503.08944 are unfounded, and we uphold the conclusions of Phys. Rev. B 107, 245423 (2023) and Nature 638, 651-655 (2025). Specifically, we show that no flaws have been identified in our estimate of the false discovery rate (FDR). We provide a point-by-point rebuttal of the comments in arXiv:2502.19560 and arXiv:2503.08944.

cond-mat.mes-hall↗

arXiv2024

InAs-Al Hybrid Devices Passing the Topological Gap Protocol

We present measurements and simulations of semiconductor-superconductor heterostructure devices that are consistent with the observation of topological superconductivity and Majorana zero modes. The devices are fabricated from high-mobility two-dimensional electron gases in which quasi-one-dimensional wires are defined by electrostatic gates. These devices enable measurements of local and non-local transport properties and have been optimized via extensive simulations to ensure robustness against non-uniformity and disorder. Our main result is that several devices, fabricated according to the design's engineering specifications, have passed the topological gap protocol defined in Pikulin et al. [arXiv:2103.12217]. This protocol is a stringent test composed of a sequence of three-terminal local and non-local transport measurements performed while varying the magnetic field, semiconductor electron density, and junction transparencies. Passing the protocol indicates a high probability of detection of a topological phase hosting Majorana zero modes as determined by large-scale disorder simulations. Our experimental results are consistent with a quantum phase transition into a topological superconducting phase that extends over several hundred millitesla in magnetic field and several millivolts in gate voltage, corresponding to approximately one hundred micro-electron-volts in Zeeman energy and chemical potential in the semiconducting wire. These regions feature a closing and re-opening of the bulk gap, with simultaneous zero-bias conductance peaks at both ends of the devices that withstand changes in the junction transparencies. The extracted maximum topological gaps in our devices are 20-60 $μ$eV. This demonstration is a prerequisite for experiments involving fusion and braiding of Majorana zero modes.

cond-mat.mes-hall↗

arXiv2022

Doubling the mobility of InAs/InGaAs selective area grown nanowires

Selective area growth (SAG) of nanowires and networks promise a route toward scalable electronics, photonics and quantum devices based on III-V semiconductor materials. The potential of high-mobility SAG nanowires however is not yet fully realized, since interfacial roughness, misfit dislocations at the nanowire/substrate interface and non-uniform composition due to material intermixing all scatter electrons. Here, we explore SAG of highly lattice-mismatched InAs nanowires on insulating GaAs(001) substrates and address these key challenges. Atomically smooth nanowire/substrate interfaces are achieved with the use of atomic hydrogen (a-H) as an alternative to conventional thermal annealing for the native oxide removal. The problem of high lattice mismatch is addressed through an In$_x$Ga$_{1-x}$As buffer layer introduced between the InAs transport channel and the GaAs substrate. The Ga-In material intermixing observed in both the buffer layer and the channel is inhibited via careful tuning of the growth temperature. Performing scanning transmission electron microscopy and x-ray diffraction analysis along with low-temperature transport measurements we show that optimized In-rich buffer layers promote high quality InAs transport channels with the field-effect electron mobility over~10000~cm$^2$V$^{-1}$s$^{-1}$. This is twice as high as for non-optimized samples and among the highest reported for InAs selective area grown nanostructures.

cond-mat.mtrl-sci↗