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Mostafa Darvishi

Publications and source records attributed to Mostafa Darvishi.

12 recordsLinked to original sources
arXiv2026

Embedded Machine Learning for Microcontroller-Class Edge Devices: Data, Feature, Evaluation, and Deployment Pipelines

Embedded machine learning moves inference from cloud services to resource-constrained devices that must acquire data, preprocess signals, run a model, and act within tight limits on memory, energy, and latency. This paper presents a systems-oriented synthesis of an embedded machine-learning workflow for microcontroller-class platforms. The emphasis is placed on engineering decisions that are often hidden in generic machine-learning introductions: sampling and buffering, feature extraction as dimensionality reduction, validation under class imbalance, model/runtime co-design, and streaming deployment. Two representative signal families are used throughout the paper. The first is inertial motion recognition, where a two-second, three-axis accelerometer window is transformed from raw samples into root-mean-square and spectral features before classification. The second is keyword spotting, where audio is sampled, anti-aliased, transformed into mel-frequency cepstral coefficients, and processed by a compact one-dimensional convolutional network. The paper concludes with practical design rules for robust on-device inference, including data curation, quantization, thresholding, scheduling, and field monitoring.

cs.LG↗
arXiv2026

In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs

Timing degradation in SRAM-based FPGAs arises from multiple physical mechanisms that manifest differently in the routing fabric, most notably power-distribution-network (PDN) marginality and configuration-induced routing perturbations. Existing in-situ timing monitors provide limited insight into the physical origin, spatial structure, or statistical characteristics of the degradation. This paper presents a scalable in-situ timing diagnosis architecture that enables fine-grained, routing-aware characterization of timing behavior directly within the FPGA fabric during normal operation. The proposed approach combines non-intrusive delay taps placed at routing switch-matrix boundaries with distributed phase-swept delay monitoring elements and centralized statistical analysis. By extracting probabilistic delay distributions rather than binary timing margins, the framework captures both mean delay shifts and timing variability across spatially distributed routing locations. Experimental results obtained on a modern SRAM-based FPGA show that PDN-induced timing degradation produces globally correlated delay shifts with minimal change in variance, whereas routing-induced perturbations exhibit localized, topology-dependent delay growth and increased timing dispersion. Spatial correlation analysis and two-dimensional correlation heatmaps further reveal distinct signatures that enable systematic differentiation between these mechanisms. The presented architecture operates concurrently with an active user design and does not require external instrumentation, radiation sources, or design modification. These results establish a practical foundation for in-situ timing diagnosis, reliability assessment, and architecture-aware timing management in large FPGA-based systems.

eess.SP↗
arXiv2026

A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation

Floating point arithmetic is costly on FPGA platforms due to wide datapaths, normalization, and carry propagation, motivating alternative numerical representations that improve throughput and efficiency. This paper presents the Hybrid Residue Floating Numerical Architecture (HRFNA), a fully specified numerical system that combines carry-free residue arithmetic with lightweight exponent-based scaling to achieve wide dynamic range, predictable error behavior, and efficient FPGA implementation. HRFNA is developed with a rigorous mathematical foundation: the hybrid number space is formally defined, correctness of arithmetic and normalization is proven, and explicit absolute and relative error bounds are derived, confining rounding to infrequent normalization events. A complete FPGA microarchitecture is presented, featuring deeply pipelined modular arithmetic, exponent management, and a CRT-based normalization engine that sustains an initiation interval of one cycle under steady-state operation. Application-level evaluation on dot products, dense matrix multiplication, and iterative Runge-Kutta ODE solvers demonstrates stable numerical behavior over long computation sequences. Implemented on a Xilinx Zynq UltraScale Plus ZCU104, HRFNA achieves up to 2.4 times higher throughput, 38 to 55 percent LUT reduction, and up to 1.9 times energy efficiency improvement compared to IEEE 754 FP32 baselines, while maintaining bounded numerical error. Comparative analysis shows that HRFNA occupies a previously unexplored design point between numerical stability, dynamic range, and hardware efficiency, making it well suited for FPGA-centric scientific and CAD-relevant computation.

cs.AR↗
arXiv2026

Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs

Selective hardening is widely employed to improve the reliability of FPGA based soft processors while limiting the overhead of full redundancy. However, existing approaches primarily rely on architectural criticality or functional fault analysis, overlooking the impact of routing dependent timing sensitivity on processor robustness. This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs. Building on recent advances in in situ timing observability, the proposed approach quantifies the statistical timing sensitivity of pipeline components under controlled routing perturbations and uses this information to guide hardening decisions. Experimental results on a RISCV processor implemented on a commercial FPGA platform show that components exhibiting higher timing fragility also demonstrate increased vulnerability to routing induced delay effects. Leveraging this correlation, the proposed selective hardening strategy achieves robustness comparable to full hardening while significantly reducing area and timing overhead. These results demonstrate that timing fragility provides a practical and effective metric for reliability aware design optimization in FPGA based processor architectures.

eess.SP↗
arXiv2025

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

This paper presents a pipeline stage resolved timing characterization of a 32-bit RISC V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC platform. A unified analysis framework is introduced that decomposes timing paths into logic, routing, and clocking components and maps them to well-defined pipeline stage transitions. This approach enables systematic comparison of timing behavior across heterogeneous implementation technologies at a microarchitectural level. Using static timing analysis and statistical characterization, the study shows that although both implementations exhibit dominant critical paths in the EX to MEM pipeline transition, their underlying timing mechanisms differ fundamentally. FPGA timing is dominated by routing parasitics and placement dependent variability, resulting in wide slack distributions and sensitivity to routing topology. In contrast, ASIC timing is governed primarily by combinational logic depth and predictable parametric variation across process, voltage, and temperature corners, yielding narrow and stable timing distributions. The results provide quantitative insight into the structural origins of timing divergence between programmable and custom fabrics and demonstrate the effectiveness of pipeline stage resolved analysis for identifying platform specific bottlenecks. Based on these findings, the paper derives design implications for achieving predictable timing closure in processor architectures targeting both FPGA and ASIC implementations.

eess.SP↗
arXiv2025

A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs

Floating point arithmetic remains expensive on FPGA platforms due to wide datapaths and normalization logic, motivating alternative representations that preserve dynamic range at lower cost. This work introduces the Hybrid Residue Floating Numerical Architecture (HRFNA), a unified arithmetic system that combines carry free residue channels with a lightweight floating point scaling factor. We develop the full mathematical framework, derive bounded error normalization rules, and present FPGA optimized microarchitectures for modular multiplication, exponent management, and hybrid reconstruction. HRFNA is implemented on a Xilinx ZCU104, with Vitis simulation, RTL synthesis, and on chip ILA traces confirming cycle accurate correctness. The architecture achieves over 2.1 times throughput improvement and 38-52 percent LUT reduction compared to IEEE 754 single precision baselines while maintaining numerical stability across long iterative sequences. These results demonstrate that HRFNA offers an efficient and scalable alternative to floating point computation on modern FPGA devices.

eess.SP↗
arXiv2025

Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies

This paper presents an in-depth analysis of timing closure challenges and constraints in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). We examine core timing principles, architectural distinctions, and design methodologies influencing timing behavior in both technologies. A case study comparing the Xilinx Kintex UltraScale+ FPGA (XCKU040) with a 7nm ASIC highlights practical timing analysis and performance trade-offs. Experimental results show ASICs achieve superior timing of 45ps setup and 35ps hold, while modern FPGAs remain competitive with 180ps setup and 120ps hold times, validating their suitability for high-performance designs.

cs.AR↗
arXiv2021

Fault-Resilient PCIe Bus with Real-time Error Detection and Correction

This paper presents a novel IP design for real-time fault/error detection and recovery on a peripheral component interconnect express (PCIe) which interfaces a host system (here a PC) to a slave design including processing system and memory transaction implemented on a Zynq Ultrascale Xilinx Kintex FPGA board (KCU105). The proposed IP design is capable of detection and correction of different types of PCIe errors on-the-fly

eess.SP↗
arXiv2020

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics

This paper presents an automated algorithm for optimum configuration of routing interconnection network in Xilinx Zynq-7000 All programmable system-on-chip (APSoC) fabrics. A method to configure circuits with optimum routing resources is presented along with their performance parameters with and without the proposed algorithm. The proposed algorithm enables full control over routing resources for using different interconnection types in order to create routing-based circuit-under-test. The algorithm proposes the routing techniques through the 2-D array of switch matrices inside the interconnection network and automatically identifies the involved programmable interconnection points associated with a node. An experimental setup is proposed to measure the performance parameters such as slack time and power with and without the applied algorithm on the APSoC routing resources. The proposed setup requires no external equipment such as manufactured equipments or external instruments for performance measurement.

cs.AR↗
arXiv2019

Linear and Nonlinear Identification of Dryer System Using Artificial Intelligence and Neural Networks

As you read these words you are using a complex biological neural network. You have a highly interconnected set of some neurons to facilitate your reading, breathing, motion and thinking. Each of your biological neurons, a rich assembly of tissue and chemistry, has the complexity, if not the speed, of a microprocessor. Some of your neural structure was with you at birth. Other parts have been established by experience.

cs.LG↗