arXiv subjects

Mostafizur Rahman

Publications and source records attributed to Mostafizur Rahman.

At least 37 records · Page 2Linked to original sources

arXiv2022

Echoes from braneworld wormholes

We have studied the stability of wormhole geometries, under massless scalar, electromagnetic and axial gravitational perturbations, in the context of higher dimensional spacetimes. Intriguingly, the construction of a wormhole spacetime in the presence of higher dimensions, known as braneworld wormholes, \emph{does not} require the existence of exotic matter fields, unlike the scenario in four spacetime dimensions. Being a nonvacuum spacetime, the effective potential experienced by the axial gravitational perturbation differs considerably from the scenarios involving black holes. In particular, the present work provides one of the first attempts to study the gravitational perturbations of the wormhole spacetimes. Our analysis, involving both analytical and numerical techniques, demonstrates that there are echoes in the time domain signal of all the perturbations and the echo time delay is intimately related to the parameters originating from higher dimensions. Thereby combining the attempt to search for wormholes and extra dimensions, with the existence of gravitational wave echoes. Implications and future directions have also been discussed.

gr-qc↗

arXiv2021

Ringdown of Charged Compact Objects using Membrane Paradigm

Although the black holes are an integral part of the standard model of astrophysics and cosmology, their existence poses some serious fundamental problems. In recent years, several horizonless compact object models were proposed to address those issues. As the gravitational wave detectors started to observe more and more merger events with a large signal-to-noise ratio, gravitational wave spectroscopy could hold the key to uncover the existence of these objects. This is because the late time ringdown signals of horizonless compact objects differ from that of the black holes. In this paper, we study the ringdown properties of charged compact objects and compare them with those obtained in the black hole scenario. Since the internal structure and the equation of state of these compact objects are largely unknown, we employ membrane paradigm to obtain appropriate boundary conditions for the perturbations of these objects. This model can describe the ringdown properties of a large variety of compact objects.

gr-qc↗

arXiv2020

Strong cosmic censorship conjecture with NUT charge and conformal coupling

Strong cosmic censorship conjecture is central to the deterministic nature of general relativity, since it asserts that given any generic initial data on a spacelike hypersurface, the future can be uniquely predicted. However, recently it has been found that for charged black holes in asymptotically de Sitter spacetimes, the metric and massless scalar fields can be extended beyond the Cauchy horizon. This spells doom on the strong cosmic censorship conjecture, which prohibits precisely this scenario. In this work we try to understand the genericness of the above situation by studying the effect of NUT charge and conformally coupled scalar field on the violation of strong cosmic censorship conjecture for charged asymptotically de Sitter black holes. We have shown that even in the presence of the NUT charge and a conformally coupled scalar field strong cosmic censorship conjecture in indeed violated for such black holes with Cauchy horizon. Moreover, the presence of conformal coupling makes the situation even worse, in the sense that the scalar field is extendible across the Cauchy horizon as a $C^{1}$ function. On the other hand, the strong cosmic censorship conjecture is respected for conformally coupled scalar field in rotating black hole spacetimes with NUT charge. This reinforces the belief that possibly for astrophysical black holes, strong cosmic censorship conjecture is respected, irrespective of the nature of the scalar field.

gr-qc↗

arXiv2020

Effect of Bi-substitution on Structural Stability and Improved Thermoelectric Performance of p-type Half-Heusler TaSbRu: A First-principles Study

Recently, Fang et al. have predicted a high ZT of 1.54 in TaSbRu alloys at 1200 K from first-principles without considering spin-orbit interaction, accurate electronic structure, details of phonon scattering, and energy-dependent holes relaxation time. Here, we report the details of structural stability and thermoelectric performance of Bi-Substituted p-type TaSbRu from first-principles calculations considering theses important parameters. This indirect bandgap semiconductor (Eg=0.8 eV by TB-mBJ+SOC) has highly dispersive and degenerate valence bands, which lead to a maximum power factor, 3.8 mWm-1K-2 at 300K. As Sb-5p has a small contribution to the bandgap formation, the substitution of Bi on the Sb site does not cause significant change to the electronic structure. Although the Seebeck coefficient increases by Bi due to slight changes in the bandgap, electrical conductivity, and hence, the power factor reduces to ~3 mW m-1K-2 at 300K (50% Bi). On the other side, lattice thermal conductivity drops effectively to 5 from 20 W/m K as Bi introduces a significant contribution in the acoustic phonon region and intensify phonon scattering. Thus, ZT value is improved through Bi-substitution, reaching 1.1 (50% Bi) at 1200 K from 0.45 (pure TaSbRu) only. Therefore, the present study suggests how to improve the TE performance of Sb-based half-Heusler compounds and TaSbRu (with 50% Bi) is a promising material for high-temperature applications.

cond-mat.mtrl-sci↗

arXiv2020

On the validity of Strong Cosmic Censorship Conjecture in presence of Dirac fields

A well posed theory of nature is expected to determine the future of an observer uniquely from a given set of appropriate initial data. In the context of general relativity, this is ensured by Penrose's strong cosmic censorship conjecture. But in recent years, several examples are found which suggest breakdown of the deterministic nature of the theory in Reissner-Nordstrom-de Sitter black holes under the influence of different fundamental fields. Nevertheless, the situation has been reassuring for the case of astrophysically meaningful Kerr-de Sitter black hole solutions which seems to respect the conjecture. However, the previous analyses were done considering only the effect of scalar fields. In this paper, we extend the study by considering Dirac fields in Kerr-de Sitter background and show that there exist a parameter space which does not respect the conjecture.

gr-qc↗

arXiv2020

Crosstalk Noise based Configurable Computing: A New Paradigm for Digital Electronics

The past few decades have seen exponential growth in capabilities of digital electronics primarily due to the ability to scale Integrated Circuits (ICs) to smaller dimensions while attaining power and performance benefits. That scalability is now being challenged due to the lack of scaled transistor performance and also manufacturing complexities [1]-[5]. In addition, the growing cyber threat in fabless manufacturing era poses a new front that modern ICs need to withstand. We present a new noise based computing where the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit programmable Boolean logic behavior. The reliance on just coupling between metal lines and not on transistors for computing, and the programmability are the foundations for better scalability, and security by obscurity. Here, we show experimental evidence of a functioning Crosstalk computing chip at 65nm technology. Our demonstration of computing constructs, gate level configurability and utilization of foundry processes show feasibility. These results in conjunction with our simulation results at 7nm for various benchmarks, which show over 48%, 57%, and 10% density, power and performance respectively, gains over equivalent CMOS in the best case, show potentials. The benefits of Crosstalk circuits and inherent programmable features set it apart and make it a promising prospect for future electronics.

cs.ET↗

arXiv2019

A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs

Crosstalk computing, involving engineered interference between nanoscale metal lines, offers a fresh perspective to scaling through co-existence with CMOS. Through capacitive manipulations and innovative circuit style, not only primitive gates can be implemented, but custom logic cells such as an Adder, Subtractor can be implemented with huge gains. Our simulations show over 5x density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper introduces the Crosstalk circuit style and a key method for large-scale circuit synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS synthesis flow by adding two extra steps: conversion of the gate-level netlist to Crosstalk implementation friendly netlist through logic simplification and Crosstalk gate mapping, and the inclusion of custom cell libraries for automated placement and layout. Our logic simplification approach first converts Cadence generated structured netlist to Boolean expressions and then uses the majority synthesis tool to obtain majority functions, which is further used to simplify functions for Crosstalk friendly implementations. We compare our approach of logic simplification to that of CMOS and majority logic-based approaches. Crosstalk circuits share some similarities to majority synthesis that are typically applied to Quantum Cellular Automata technology. However, our investigation shows that by closely following Crosstalk's core circuit styles, most benefits can be achieved. In the best case, our approach shows 36% density improvements over majority synthesis for MCNC benchmark.

cs.ET↗

arXiv2019

Fate of Strong Cosmic Censorship Conjecture in Presence of Higher Spacetime Dimensions

Strong cosmic censorship conjecture has been one of the most important leap of faith in the context of general relativity, providing assurance in the deterministic nature of the associated field equations. Though it holds well for asymptotically flat spacetimes, a potential failure of the strong cosmic censorship conjecture might arise for spacetimes inheriting Cauchy horizon along with a positive cosmological constant. We have explicitly demonstrated that violation of the censorship conjecture holds true in the presence of a Maxwell field even when higher spacetime dimensions are invoked. In particular, for a higher dimensional Reissner-Nordström-de Sitter black hole the violation of cosmic censorship conjecture is at a larger scale compared to the four dimensional one, for certain choices of the cosmological constant. On the other hand, for a brane world black hole, the effect of extra dimension is to make the violation of cosmic censorship conjecture weaker. For rotating black holes, intriguingly, the cosmic censorship conjecture is always respected even in presence of higher dimensions. A similar scenario is also observed for a rotating black hole on the brane.

gr-qc↗

arXiv2019

Astrophysical Signatures of Black holes in Generalized Proca Theories

Explaining the late time acceleration is one of the most challenging tasks for theoretical physicists today. Infra-red modification of Einstein's general theory of relativity (GR) is a possible route to model late time acceleration. In this regard, vector-tensor theory as a part of gravitational interactions on large cosmological scales, has been proposed recently. This involves generalization of massive Proca lagrangian in curved space time. Black hole solutions in such theories have also been constructed. In this paper, we study different astrophysical signatures of such black holes. We first study the strong lensing and time delay effect of such static spherically symmetric black hole solutions, in particular for the case of gravitational lensing of the star S2 by Sagittarius A* at the centre of Milky Way. We also construct the rotating black hole solution from this static spherically symmetric solution in Proca theories using the Newman-Janis algorithm and subsequently study lensing, time delay and black hole shadow effect in this rotating black hole space time. We discuss the possibility of detecting Proca hair in future observations.

gr-qc↗

arXiv2018

Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits

Truly polymorphic circuits, whose functionality/circuit behavior can be altered using a control variable, can provide tremendous benefits in multi-functional system design and resource sharing. For secure and fault tolerant hardware designs these can be crucial as well. Polymorphic circuits work in literature so far either rely on environmental parameters such as temperature, variation etc. or on special devices such as ambipolar FET, configurable magnetic devices, etc., that often result in inefficiencies in performance and/or realization. In this paper, we introduce a novel polymorphic circuit design approach where deterministic interference between nano-metal lines is leveraged for logic computing and configuration. For computing, the proposed approach relies on nano-metal lines, their interference and commonly used FETs, and for polymorphism, it requires only an extra metal line that carries the control signal. In this paper, we show a wide range of crosstalk polymorphic (CT-P) logic gates and their evaluation results. We also show an example of a large circuit that performs both the functionalities of multiplier and sorter depending on the configuration signal. Our benchmarking results are presented in this paper. For CT-P, the transistor count was found to be significantly less compared to other existing approaches, ranging from 25% to 83%. For example, CT-P AOI21-OA21 cell show 83%, 85% and 50% transistor count reduction, and MultiplierSorter circuit show 40%, 36% and 28% transistor count reduction with respect to CMOS, genetically evolved, and ambipolar transistor based polymorphic circuits respectively.

cs.AR↗

arXiv2018

A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks

The CMOS integrated chips at advanced technology nodes are becoming more vulnerable to various sources of faults like manufacturing imprecisions, variations, aging, etc. Additionally, the intentional fault attacks (e.g., high power microwave, cybersecurity threats, etc.) and environmental effects (i.e., radiation) also pose reliability threats to integrated circuits. Though the traditional hardware redundancy-based techniques like Triple Modular Redundancy (TMR), Quadded (QL) Logic etc. mitigate the risk to some extent, they add huge hardware overhead and are not very effective. Truly polymorphic circuits that are inherently capable of achieving multiple functionalities in a limited footprint could enhance the faultresilience/recovery of the circuits with limited overhead. We demonstrate a novel crosstalk logic based polymorphic circuit approach to achieve compact and efficient fault resilient circuits. We show a range of polymorphic primitive gates and their usage in a functional unit. The functional unit is a single arithmetic circuit that is capable of delivering Multiplication/Sorting/Addition output depending on the control inputs. Using such polymorphic computing units in an ALU would imply that a correct path for functional output is possible even when 2/3rd of the ALU is damaged. Our comparison results with respect to existing polymorphic techniques and CMOS reveal 28% and 62% reduction in transistor count respectively for the same functionalities. In conjunction with fault detection algorithms, the proposed polymorphic circuit concept can be transformative for fault tolerant circuit design directions with minimum overhead.

cs.AR↗

arXiv2018

Black Hole Topology in $f(R)$ Gravity

Hawking's topology theorem in general relativity restricts the cross-section of the event horizon of a black hole in $3+1$ dimension to be either spherical or toroidal. The toroidal case is ruled out by the topology censorship theorems. In this article, we discuss the generalization of this result to black holes in $f(R)$ gravity in $3+1$ and higher dimensions. We obtain a sufficient differential condition on the function $f'(R)$, which restricts the topology of the horizon cross-section of a black hole in $f(R)$ gravity in $3+1$ dimension to be either $S^2$ or $S^1 \times S^1$. We also extend the result to higher dimensional black holes and show that the same sufficient condition also restricts the sign of the Yamabe invariant of the horizon cross-section.

gr-qc↗

arXiv2018

Thermal Management in Fine-Grained 3-D Integrated Circuits

For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting nano pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.

cs.ET↗

arXiv2017

Cost Modeling and Projection for Stacked Nanowire Fabric

To continue scaling beyond 2-D CMOS with 3-D integration, any new 3-D IC technology has to be comparable or better than 2-D CMOS in terms of scalability, enhanced functionality, density, power, performance, cost, and reliability. Transistor-level 3-D integration carries the most potential in this regard. Recently, we proposed a stacked horizontal nanowire based transistor-level 3-D integration approach, called SN3D [1][2] that solves scaling challenges and achieves tremendous benefits with respect to 2-D CMOS while keeping manageable thermal profile. In this paper, we present the cost analysis of SN3D and show comparison with 2-D CMOS (2D), conventional TSV based 3-D (T3D) and Monolithic 3-D integrations (M3D). In our cost model, we capture the implications of manufacturing, circuit density, interconnects, bonding and heat in determining die cost, and evaluate how cost scales as transistor count increases. Since SN3D is a new 3-D IC fabric, based on our proposed manufacturing pathway[1] we assumed complexity of fabrication steps as proportionality constants in our cost estimation model. Our analysis revealed 86%, 72% and 74% reduction in area; 55%, 43% and 43% reduction in interconnects distribution and total interconnect length for SN3D, which largely contributed to 70%, 67% and 68% reduction in cost in comparison to 2D, T3D and M3D respectively.

cs.ET↗

arXiv2016

Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2D in terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6x lower routing demand against T-MI with no routing congestion (routing demand to resource ratio < 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3x lower power and 11x higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2x density improvement over 2D CMOS.

cs.ET↗

arXiv2016

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Parallel and monolithic 3D integration directions offer pathways to realize 3D integrated circuits (ICs) but still lead to layer-by-layer implementations, each functional layer being composed in 2D first. This mindset causes challenging connectivity, routing and layer alignment between layers when connected in 3D, with a routing access that can be even worse than 2D CMOS, which fundamentally limits their potential. To fully exploit the opportunities in the third dimension, we propose Skybridge-3D-CMOS (S3DC), a fine-grained 3D integration approach that is directly composed in 3D, utilizing the vertical dimension vs. using a layer-by-layer assembly mindset. S3DC uses a novel wafer fabric creation with direct 3D design and connectivity in the vertical dimension. It builds on a uniform vertical nanowire template that is processed as a single wafer; it incorporates specifically architected structures for realizing devices, circuits, and heat management directly in 3D. Novel 3D interconnect concepts, including within the silicon layers, enable significantly improved routing flexibility in all three dimensions and a high-density 3D design paradigm overall. Intrinsic components for fabric-level 3D heat management are introduced. Extensive bottom-up simulations and experiments have been presented to validate the key fabric-enabling concepts. Evaluation results indicate up to 40x density and 10x performance-per-watt benefits against conventional 16-nm CMOS for the circuits studied; benefits are also at least an order of magnitude beyond what was shown to be possible with other 3D directions.

cs.ET↗

arXiv2015

Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric

At sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3D has been long sought as a possible pathway to continue scaling, however, intrinsic requirements of CMOS are not compatible for fine-grained 3D integration. We proposed a truly fine-grained 3D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3D compatible manner. At the core of Skybridge assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping are performed prior to any functionalization and their precision requirements are significantly reduced. This paper introduces Skybridge manufacturing pathway that is developed based on extensive process, device simulations and experimental metrology, and uses established processes. Experimental demonstrations of key process steps are also shown.

cs.OH↗

arXiv2015

Self-similar Magneto-electric Nanocircuit Technology for Probabilistic Inference Engines

Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in CMOS implementations. In this paper, we present a magneto-electric probabilistic technology framework for implementing probabilistic reasoning functions. The technology leverages Straintronic Magneto-Tunneling Junction (S-MTJ) devices in a novel mixed-signal circuit framework for direct computations on probabilities while enabling in-memory computations with persistence. Initial evaluations of the Bayesian likelihood estimation operation occurring during Bayesian Network inference indicate up to 127x lower area, 214x lower active power, and 70x lower latency compared to an equivalent 45nm CMOS Boolean implementation.

cs.ET↗