arXiv subjects

Murthy Durbhakula

Publications and source records attributed to Murthy Durbhakula.

4 recordsLinked to original sources

arXiv2019

Branch prediction related Optimizations for Multithreaded Processors

Major chip manufacturers have all introduced Multithreaded processors. These processors are used for running a variety of workloads. Efficient resource utilization is an important design aspect in such processors. Depending on the workload, mis-speculated execution can severely impact resource utilization and power utilization. In general, compared to a uniprocessor, a multithreaded processor may have better tolerance towards mis-speculation. However there can still be phases where even a multi-threaded processor performance may get impacted by branch induced mis-speculation. In this paper I propose monitoring the branch predictor behavior of various hardware threads running on the multi-threaded processor and use that information as a feedback to the thread arbiter/picker which schedules the next thread to fetch instructions from. If I find that a particular thread is going through a phase where it is consistently mis-predicting its branches and its average branch misprediction stall is above a specific threshold then I temporarily reduce the priority for picking that thread. I do a qualitative comparison of various solutions to the problem of resource inefficiency caused due to mis-speculated branches in multithreaded processors. This work can be extended by doing a quantitative evaluation.

cs.PF↗

arXiv2019

MLP Aware Scheduling Techniques in Multithreaded Processors

Major chip manufacturers have all introduced Multithreaded processors. These processors are used for running a variety of workloads. Efficient resource utilization is an important design aspect in such processors. Particularly, it is important to take advantage of available memory-level parallelism(MLP). In this paper I propose a MLP aware operating system (OS) scheduling algorithm for Multithreaded Multi-core processors. By observing the MLP available in each thread and by balancing it with available MLP resources in the system the OS will come up with a new schedule of threads for the next quantum that could potentially improve overall performance. We do a qualitative comparison of our solution with other hardware and software techniques. This work can be extended by doing a quantitative evaluation and by further refining the scheduling optimization.

cs.PF↗

arXiv2019

Cache Optimization for Memory Intensive Workloads on Multi-socket Multi-core servers

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. Depending on the application that is run on the system, remote memory accesses can impact overall performance. This paper presents a cache optimization that can cut down remote DRAM accesses. By keeping track of remote cache lines loaded from remote DRAM and by biasing the cache replacement policy towards such remote DRAM cache lines the number of cache misses are reduced. This in turn results in improvement of overall performance. I present the design details in this paper. I do a qualitative comparison of various solutions to the problem of performance impact of remote DRAM accesses. This work can be extended by doing a quantitative evaluation and by further refining cache optimization.

cs.DC↗

arXiv2018

OS Scheduling Algorithms for Memory Intensive Workloads in Multi-socket Multi-core servers

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are routinely used for running various server applications. Depending on the application that is run on the system, remote memory accesses can impact overall performance. This paper presents a new operating system (OS) scheduling optimization to reduce the impact of such remote memory accesses. By observing the pattern of local and remote DRAM accesses for every thread in each scheduling quantum and applying different algorithms, we come up with a new schedule of threads for the next quantum. This new schedule potentially cuts down remote DRAM accesses for the next scheduling quantum and improves overall performance. We present three such new algorithms of varying complexity followed by an algorithm which is an adaptation of Hungarian algorithm. We used three different synthetic workloads to evaluate the algorithm. We also performed sensitivity analysis with respect to varying DRAM latency. We show that these algorithms can cut down DRAM access latency by up to 55% depending on the algorithm used. The benefit gained from the algorithms is dependent upon their complexity. In general higher the complexity higher is the benefit. Hungarian algorithm results in an optimal solution. We find that two out of four algorithms provide a good trade-off between performance and complexity for the workloads we studied.

cs.DC↗