arXiv subjects

Naize Yang

Publications and source records attributed to Naize Yang.

3 recordsLinked to original sources

arXiv2026

A Neuroprosthetic SoC Featuring Rapid Local Sensory Feedback with On-Chip Unsupervised Multi-Class Spike Sorting

This letter presents a 65 nm neuroprosthetic system-on-chip (SoC) featuring a rapid feedback pathway from motor recording to sensory stimulation. To enable low-latency sensory mapping modulated by individual-neuron firing rates, the SoC integrates a mixed-signal unsupervised spike-sorting module with stimulation-artifact rejection, a programmable sliding-window firing-rate calculator, and a closed-loop controller for adapting stimulation parameters. The spike-sorting module combines event-driven analog feature extraction with Manhattan-distance-based digital clustering while consuming 1.6 $μ$W/channel. On the Quiroga Difficult-1 benchmark, it achieves 94.58% three-class accuracy, with only a 0.4% reduction when stimulation artifacts are introduced at 20% of the spike count. The closed-loop controller supports polynomial and logarithmic mapping functions and incorporates Mitchell's approximation for power saving. The SoC is fully characterized on the bench and in vivo.

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arXiv2026

FPGA Acceleration of CNN-BiLSTM for EEG-Based Sleep Staging Featuring FFT-Based Non-Unit Stride Fast Convolution

Deep learning (DL) models for real-time wearable sleep staging often rely on long-kernel temporal convolutions, a requirement that current accelerators struggle to support efficiently. To overcome this, we present an FPGA-based CNN-BiLSTM accelerator that incorporates several algorithm-hardware co-design techniques to enable efficient edge inference. Central to this design is an FFT-based non-unit stride fast convolution, which performs accumulation in the frequency domain to enable a single IFFT per block, reducing post-processing complexity to $O(N\log N)$. On the target long-kernel convolution layer, this yields a 20.5$\times$ reduction in arithmetic operations. Power-of-two quantization is applied across the pipeline, including FFT-based convolution and BiLSTM activations, with an average accuracy degradation of only 0.11% relative to the floating-point baseline across all subjects on the public MASS-SS3 dataset. Additional optimizations, including block convolution, depth-first execution, and hardware engine reuse minimize memory access and enhance resource utilization. The accelerator, implemented on a Xilinx Zynq-7000 FPGA, operates at 10 MHz and consumes 11 mW of dynamic power including data handling and configuration overhead from a microcontroller. The design achieves a DSP power efficiency of 0.91 GOPS/W/DSP using only 4 DSPs, demonstrating scalable and energy-efficient DL acceleration for sleep staging that can be extended to other wearable applications.

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arXiv2022

A Closed-loop Sleep Modulation System with FPGA-Accelerated Deep Learning

Closed-loop sleep modulation is an emerging research paradigm to treat sleep disorders and enhance sleep benefits. However, two major barriers hinder the widespread application of this research paradigm. First, subjects often need to be wire-connected to rack-mount instrumentation for data acquisition, which negatively affects sleep quality. Second, conventional real-time sleep stage classification algorithms give limited performance. In this work, we conquer these two limitations by developing a sleep modulation system that supports closed-loop operations on the device. Sleep stage classification is performed using a lightweight deep learning (DL) model accelerated by a low-power field-programmable gate array (FPGA) device. The DL model uses a single channel electroencephalogram (EEG) as input. Two convolutional neural networks (CNNs) are used to capture general and detailed features, and a bidirectional long-short-term memory (LSTM) network is used to capture time-variant sequence features. An 8-bit quantization is used to reduce the computational cost without compromising performance. The DL model has been validated using a public sleep database containing 81 subjects, achieving a state-of-the-art classification accuracy of 85.8% and a F1-score of 79%. The developed model has also shown the potential to be generalized to different channels and input data lengths. Closed-loop in-phase auditory stimulation has been demonstrated on the test bench.

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