arXiv subjects

Nandakumar Nambath

Publications and source records attributed to Nandakumar Nambath.

6 recordsLinked to original sources

arXiv2024

Machine Learning Driven Global Optimisation Framework for Analog Circuit Design

We propose a machine learning-driven optimisation framework for analog circuit design in this paper. The primary objective is to determine the device sizes for the optimal performance of analog circuits for a given set of specifications. Our methodology entails employing machine learning models and spice simulations to direct the optimisation algorithm towards achieving the optimal design for analog circuits. Machine learning based global offline surrogate models, with the circuit design parameters as the input, are built in the design space for the analog circuits under study and is used to guide the optimisation algorithm, resulting in faster convergence and a reduced number of spice simulations. Multi-layer perceptron and random forest regressors are employed to predict the required design specifications of the analog circuit. Since the saturation condition of transistors is vital in the proper working of analog circuits, multi-layer perceptron classifiers are used to predict the saturation condition of each transistor in the circuit. The feasibility of the candidate solutions is verified using machine learning models before invoking spice simulations. We validate the proposed framework using three circuit topologies--a bandgap reference, a folded cascode operational amplifier, and a two-stage operational amplifier. The simulation results show better optimum values and lower standard deviations for fitness functions after convergence. Incorporating the machine learning-based predictions proposed in the optimisation method has resulted in the reduction of spice calls by 56%, 59%, and 83% when compared with standard approaches in the three test cases considered in the study.

cs.NE↗

arXiv2023

Performance Evaluation of Evolutionary Algorithms for Analog Integrated Circuit Design Optimisation

An automated sizing approach for analog circuits using evolutionary algorithms is presented in this paper. A targeted search of the search space has been implemented using a particle generation function and a repair-bounds function that has resulted in faster convergence to the optimal solution. The algorithms are tuned and modified to converge to a better optimal solution with less standard deviation for multiple runs compared to standard versions. Modified versions of the artificial bee colony optimisation algorithm, genetic algorithm, grey wolf optimisation algorithm, and particle swarm optimisation algorithm are tested and compared for the optimal sizing of two operational amplifier topologies. An extensive performance evaluation of all the modified algorithms showed that the modifications have resulted in consistent performance with improved convergence for all the algorithms. The implementation of parallel computation in the algorithms has reduced run time. Among the considered algorithms, the modified artificial bee colony optimisation algorithm gave the most optimal solution with consistent results across multiple runs.

cs.NE↗

arXiv2023

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.

eess.SY↗

arXiv2021

Area Optimisation of Two Stage Miller Compensated Op-Amp in 65 nm Using Hybrid PSO

Analog circuit design can be formulated as a non-linear constrained optimisation problem that can be solved using any suitable optimisation algorithms. Different optimisation techniques have been reported to reduce the design time of analog circuits. A hybrid particle swarm optimisation algorithm with linearly decreasing inertia weight for the optimisation of analog circuit design is proposed in this study. The proposed method is used to design a two-stage operational amplifier circuit with Miller compensation. The results show that the proposed optimisation method can substantially reduce the design time needed for analog circuits.

cs.ET↗

arXiv2020

All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this work, we show that these signals can instead be processed in the analog domain itself, which can significantly reduce the power consumption as well as the complexity of the receiver. The first all-analog adaptive equalizer for receivers of coherent dual-polarization optical links has been presented with its detailed architecture and measurement results. The proof-of-concept equalizer uses the constant modulus algorithm for blind adaptation of its weight coefficients to implement a 4x4 2-tap FIR filter in 130 nm SiGe BiCMOS technology. Its functionality is evaluated experimentally for 40 Gb /s data rate and 10 km standard single-mode fiber channel. This demonstration shows that the use of all-analog processing for short-reach data-center interconnects is feasible and is a much simpler solution than the use of the high-speed ADC+DSP based approach. Moreover, when implemented in advanced CMOS or FinFET technologies, the power consumption of the equalizer is expected to be significantly lower than the DSP based implementations in similar process technologies.

eess.SP↗

arXiv2019

Demonstration of an LO-less, DSP-free QPSK Receiver for Data Center Interconnects

We present the first demonstration of a local oscillator (LO)-less digital signal processing (DSP)-free coherent receiver for high-capacity short distance optical links. Experimental results with an analog domain constant modulous algorithm (CMA)-based equalizer chip for the self-homodyne quadrature phase shift keying (SH-QPSK) system validate the employability of an all-analog and LO-less receiver for low-power interconnects.

eess.SP↗