arXiv subjects

Nashrah Afroze

Publications and source records attributed to Nashrah Afroze.

5 recordsLinked to original sources

arXiv2026

Engineering Wake-Up-Free Ferroelectric Capacitors with Enhanced High-Temperature Reliability

We systematically explore the design space of ferroelectric hafnium-zirconium oxide (H0.5Z0.5O or HZO) heterostructures for reliable high temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to 125C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85-125C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WOx) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiOxNy interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.

cond-mat.mtrl-sci↗

arXiv2026

Sub-nm2 ferroelectric domains via charged 180 degree walls in ZrO2

Flat phonon bands in fluorite ferroelectrics (HfO2 or ZrO2) shrink polar domains laterally to an irreducible half-unit-cell width (0.27 nm) within which the vertical arrangement of dipoles is expected to remain uniform. We report on the direct observation of nonuniform and nearly discrete vertical arrangements of dipoles in ZrO2 thin films consisting of closely spaced head-to-head (HH) and tail-to-tail (TT) charged 180 degree walls, each exhibiting a distinct bulk-like structure. These charged domain walls (CDWs) further compress the irreducibly narrow, laterally stacked domains vertically to a thickness of 1-2.75 nm, yielding in-plane domains with sub-nm2 footprints-among the smallest ever reported for any ferroelectric material. The HH and TT walls form due to their flat longitudinal optical (LO) polar bands and are electrostatically stabilized by bound-charge compensation via interstitial oxygen atoms, which act as natural structural defects at the HH walls. Moreover, these walls are predicted to be conducting and to exhibit ultralow propagation barriers, with HH walls (1.6 meV) being far more mobile than TT walls (22.3 meV), indicating strong potential for low-voltage, domain-wall-based nanoelectronics.

cond-mat.mtrl-sci↗

arXiv2026

ALD-Derived WO3-x Leads to Nearly Wake-Up-Free Ferroelectric Hf0.5Zr0.5O2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics-either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures such as 125C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO2-based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO3-x) layer-known as an oxygen reservoir-and carefully tuning its oxygen content, ultra-thin Hf0.5Zr0.5O2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 105 to only 10 at 125C- a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory calculations reveal that WO3 enhances the stability of the ferroelectric orthorhombic phase at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap, and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

cond-mat.mtrl-sci↗

arXiv2026

The First Switch Effect in Ferroelectric Field-Effect Transistors

In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the 'First Switch Effect'. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.

cond-mat.mtrl-sci↗

arXiv2025

Hf/Zr Superlattice-Based High-\k{appa} Gate Dielectrics with Dipole Layer Engineering for Advanced CMOS

Advanced logic transistors require gate dielectrics that achieve sub-nanometer equivalent oxide thickness (EOT), suppress leakage, and satisfy three key requirements: (i) compatibility with RMG-like high-temperature processing, (ii) sufficient Vth tunability for multi-Vth design, and (iii) high device reliability. However, meeting all of these requirements simultaneously has been difficult with conventional high-k systems. In this work, we demonstrate that Hf/Zr-based gate stacks quantitatively satisfy these conditions. After a 700 C N2 anneal, the HZH superlattice achieves an EOT of 7.3 A, lower than conventional HfO2-only stacks (8.5 A) while maintaining comparable leakage. Embedding a 3 A Al2O3 dipole within an HfO2/ZrO2/HfO2 superlattice (HZHA) breaks the conventional dipole trade-off, achieving an EOT of 8.4 A, lower than the 9.0 A of a standard HfO2/Al2O3 stack, while providing a flatband voltage shift greater than 200 mV, thereby enabling multi-Vth tuning without compromising scaling. Furthermore, under -2 V negative-bias temperature stress at 125 C for 100 s, HZHA and HA exhibit comparable flatband voltage drifts of 87 mV and 97 mV, respectively, confirming that strong Vth tunability and sub-nanometer EOT can be achieved without compromising stability. In addition to these quantitative advances, this study reveals previously unreported physical insights into dipole behavior and interfacial diffusion in ultrathin Hf/Zr multilayers. These results establish HZHA as an RMG-compatible, Vth-tunable, low-EOT dielectric platform capable of supporting logic scaling beyond the 1 nm frontier.

cond-mat.mes-hall↗