Zero-Instruction Sensor Reads: Register-Mapped Peripherals and Hardware PWM on a Five-Stage Soft Processor
We present a case study in application-driven specialization of a five-stage soft processor, evaluated on the inner control loop of a reaction-wheel self-balancing bicycle. Starting from a custom 32-bit RISC core in the MIPS tradition, we specialize the design in two ways. First, two frequently accessed peripheral inputs are mapped directly into architectural register state, written every cycle by hardware and owned exclusively through the register file's write-port structure rather than by arbitration. Second, four periodic PWM channels are offloaded to hardware and driven continuously from four exported registers, removing periodic actuation from software entirely. Because peripheral values are addressable as ordinary register operands, all ten sensor reads in the control loop cost no dedicated instruction and no dedicated cycle, folding into arithmetic that executes anyway; the memory-mapped equivalent requires an explicit load per snapshot and costs five extra instructions and cycles. The actuation path likewise removes waveform maintenance from software entirely. We report two configurations, because the extensions and the single-cycle array multiplier they were deployed alongside are not present together in a single archived build: an archived configuration, whose worst-case loop is 91 cycles, and the integrated configuration matching the deployed system, at 43 cycles. Against a 20 ms actuation frame these are margins of roughly 7,300x and 15,000x. The deadline is met by so wide a margin in either case that the specialization was not necessary for real-time compliance; its value lies in instruction count and software simplicity, not in determinism, which an on-chip single-cycle I/O region already provides. The zero-instruction sensor read is independent of that choice: the multiplier cannot affect whether a peripheral read needs an instruction of its own.