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Navakanta Bhat

Publications and source records attributed to Navakanta Bhat.

20 records · Page 2Linked to original sources

Intrinsic Limits of Subthreshold Slope in Biased Bilayer Graphene Transistor

In this work, we investigate the intrinsic limits of subthreshold slope in a dual gated bilayer graphene transistor using a coupled self-consistent Poisson-bandstructure solver. We benchmark the solver by matching the bias dependent bandgap results obtained from the solver against published experimental data. We show that the intrinsic bias dependence of the electronic structure and the self-consistent electrostatics limit the subthreshold slope obtained in such a transistor well above the Boltzmann limit of 60mV/decade at room temperature, but much below the results experimentally shown till date, indicating room for technological improvement of bilayer graphene.

cond-mat.mes-hall↗

HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET

In this letter we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of a HEMT and a FinFET, to obtain excellent performance and good off state control. Followed by the description of the design, 3D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and non-planar Si NMOSFET data of comparable gate length using standard benchmarking techniques.

cond-mat.mes-hall↗