arXiv subjects

Naveen Kadayinti

Publications and source records attributed to Naveen Kadayinti.

6 recordsLinked to original sources

arXiv2026

A High Input Impedance Chopper Stabilized Amplifier Based On Charge Conservation

Chopper stabilized amplifiers are popularly used for realizing amplifiers with low offset and for rejecting flicker noise. One of the main limitations of these amplifiers is the low Input Impedance (Zin) produced by the switch capacitor input network. Zin here is resistive due to the switch capacitor action and is inversely proportional to the product of Chopping frequency (Fch) and Input Capacitance (Ci). Since Fch should be greater than the flicker noise corner frequency, this results in a low Zin. When interfacing sensors with high Sensor Output Impedance (Zo), chopper stabilized amplifiers load the sensors resulting in reduced sensitivity. This paper presents a novel input impedance boosting technique - Differential capacitor flipping technique for chopper based Capacitively Coupled Instrumentation Amplifier (CCIA), which prevents discharge and recharge of Ci's in every cycle by reconfiguring the capacitor positions while preserving the chopping operation. This ideally results in a purely capacitive Zin which is independent of Fch. The proposed architecture is used to demonstrate Electrocardiogram (ECG) signal acquisition with dry electrodes that have Zo in the order of a few Mega Ohms. This circuit implemented in TSMC 65 nm CMOS technology node features Zin of 21 GOhms at DC. The circuit has a power consumption of 2.6E(-6)W (2.8E(-6)W including clock generation circuits), with 7.2E(-6)Vrms (1 Hz-150 Hz) of total integrated input referred noise. ~

eess.SP↗

arXiv2020

Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits

This paper shows how the input offset of sampling flip-flops in the Alexander phase detector affects the jitter transfer from data to the recovered clock in a clock data recovery circuit. The Alexander phase detector samples the data at both the edges of the clock in order to recover the data, as well as the clock timing information. The timing information is used in a clock recovery circuit, which is basically a PLL or a DLL. Once the PLL (or DLL) is locked, the phase detector samples the data at the center of the eye as well as at the data transitions. It is shown how the offset of the sampling flip-flop that samples the data at its transitions influences the jitter transfer from data to the recovered clock. Importantly, it is shown that zero offset is not always the best case. The effect is studied for different levels of data dependent jitter. The mechanism of this phenomenon is explained and the predictions are supported with simulations. The paper also discusses a tracking circuit that keeps the offset at the minimum jitter point.

eess.SP↗

arXiv2019

Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (i) data dependent jitter, (ii) random jitter, and (iii) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.

cs.ET↗

arXiv2017

Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers

A decision feedback circuit with integrated offset compensation is presented in this paper. The circuit is built around the sense amplifier comparator. The feedback loop is closed around the first stage of the comparator resulting in minimum loop latency. The feedback loop is implemented using a switched capacitor network that picks from one of pre-computed voltages to be fed back. The comparator's offset that is to be compensated for, is added in the same path. Hence, an extra offset correction input is not required. The circuit is used as a receiver for a 10 mm low swing interconnect implemented in UMC 130 nm CMOS technology. The circuit is tested at a frequency of 1 GHz and it consumes 145 $μ$A from a 1.2V supply at this frequency.

cs.AR↗

arXiv2015

Testable Design of Repeaterless Low Swing On-Chip Interconnect

Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.

cs.AR↗

arXiv2015

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop. The picked phase is then further fine tuned by an analog voltage controlled delay to position the sampling clock at the center of the eye. A clock domain transfer circuit then transfers the sampled data to the receiver clock domain with a maximum latency of three clock cycles. The proposed synchronizer has been designed and fabricated in 130 nm UMC MM CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate of 1.3 Gbps. Further, the proposed synchronizer has been designed and simulated in TSMC 65 nm CMOS technology. Post layout simulations show that the synchronizer consumes 1.5 mW from a 1 V supply, at a data rate of 4 Gbps in this technology.

cs.AR↗