arXiv subjects

Neil Dilley

Publications and source records attributed to Neil Dilley.

3 recordsLinked to original sources

arXiv2026

Spin Vector Control for Heisenberg-Inspired Probabilistic Computing

Probabilistic bits (p-bits) have emerged as a cornerstone of probabilistic computing, enabling energy-efficient hardware implementation for probabilistic inference and combinatorial optimization. A critical challenge in advancing this field beyond binary p-bits lies in realizing and manipulating vector spin information, essential for mapping complex energy-based models such as the Heisenberg Hamiltonian.Here, we demonstrate a spintronic platform capable of real-space vector summation by using dual ferromagnetic spin injections into a monolayer graphene channel. By electrically tuning the spin polarization through independently controlled injection currents, we achieve continuous control over the magnitude and direction of the resulting spin accumulation vector. Experimental observations, supported by theoretical vector summation models and spin-circuit simulations, reveal coherent vector interactions and angular tunability of the spin state. This approach enables direct implementation of vector-based spin logic and lays the groundwork for mapping classical Heisenberg models using stochastic low-barrier magnets. Our results establish a scalable pathway for realizing probabilistic spin circuits based on two-dimensional materials, offering new opportunities for low-power, non-Boolean computing architectures.

cond-mat.mes-hall↗

arXiv2026

Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit

Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips.

cs.ET↗

arXiv2023

Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs

Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional CMOS-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic-bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic Magnetic Tunnel Junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, through integrating stochastic MTJs with 2D-MoS$_{2}$ FETs, the first on-chip realization of a key p-bit building block displaying voltage-controllable stochasticity is demonstrated. In addition, supported by circuit simulations, this work provides a careful analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. This understanding of the interplay between the characteristics of the transistors and the MTJ is vital for the construction of a fully functioning p-bit, making the design rules presented in this article key for future experimental implementations of scaled on-chip p-bit networks.

cond-mat.mes-hall↗