arXiv subjects

Nicholas Zogbi

Publications and source records attributed to Nicholas Zogbi.

3 recordsLinked to original sources

arXiv2026

Synaptic Multi-Weight Wafer-Scale Domain Wall Magnetic Tunnel Junctions Driven by Spin Orbit Torque

Spintronic synaptic devices based on magnetic random access memory (MRAM) are a rapidly evolving class within the analog neuromorphic architecture. However, obtaining the multi-weight or analog behavior desired for improved neural network inference accuracy in scaled MRAM remains a challenge. In this study, we demonstrate and tune up to eight distinct resistance levels in 300 mm wafer-scale magnetic tunnel junction artificial synapses driven by spin orbit torque. By varying the applied in-plane field, multi-weight resistance states emerge through domain wall nucleation and pinning. These multi-weight states appear stochastically and can be addressed with an iterative programming algorithm to program a specific resistance. Electromagnetic simulations indicate the multiple states are due to domain wall nucleation mediated by in-plane field and applied voltage. Implementation of the measured multi-weight devices in a neural network yields a 96.1% inference accuracy using the MNIST dataset if all devices provide the same number of multi-weight states. When experimental device-to-device variation is included, the accuracy is 48.6%. Overall, this work demonstrates a route towards multi-weight artificial synapse MRAM, establishing a path towards scalable neuromorphic systems based on spintronics.

cond-mat.mes-hall↗

arXiv2026

Octupole-driven spin torque switching of antiferromagnetic tunnel junctions

Magnetic tunnel junctions (MTJs) based on ferromagnets are canonical devices in spintronics, with wide-ranging applications in data storage, computing, and sensing. They simultaneously exhibit mechanisms for electrical detection and control of magnetic order through the tunneling magnetoresistance (TMR) and spin-transfer torque (STT) effects, respectively. It was long assumed that neither of these effects could be sizeable in all-antiferromagnetic tunnel junctions (AATJs), since they exhibit no net magnetization. Recently, however, it was shown that AATJs based on chiral antiferromagnets do exhibit TMR due to their non-relativistic momentum-dependent spin polarization and cluster magnetic octupole moment (CMO), which are manifestations of their spin-split band structure. However, the reciprocal effect, i.e., the antiferromagnetic counterpart of STT, has been assumed non-existent due to the total electric current being spin-neutral. Here, we report nanoscale AATJs exhibiting this reciprocal effect, which we term octupole-driven spin-transfer torque (OTT). We demonstrate current-induced OTT switching of PtMn3|MgO|PtMn3 AATJs, exhibiting a TMR value of 363% at room temperature and switching current densities of the order of 10 MA/cm2. Our theoretical modeling explains the origin of OTT in terms of the imbalance between intra- and inter-sublattice spin currents across the AATJ, and equivalently, in terms of the non-zero net cluster octupole polarization of each PtMn3 layer. This work establishes a new materials platform for antiferromagnetic spintronics and provides a pathway towards deeply scaled magnetic memory and room-temperature terahertz technologies.

cond-mat.mtrl-sci↗

arXiv2023

Parallel Matrix Multiplication Using Voltage Controlled Magnetic Anisotropy Domain Wall Logic

The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device that can simultaneously store data and perform computations. These three-terminal devices are promising for digital logic due to their nonvolatility, low-energy operation, and radiation hardness. Here, we augment the DW-MTJ logic gate with voltage controlled magnetic anisotropy (VCMA) to improve the reliability of logical concatenation in the presence of realistic process variations. VCMA creates potential wells that allow for reliable and repeatable localization of domain walls. The DW-MTJ logic gate supports different fanouts, allowing for multiple inputs and outputs for a single device without affecting area. We simulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) units with 4-bit and 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates to enable fine-grained pipelining and high parallelism. The DW-MTJ systolic array provides comparable throughput and efficiency to state-of-the-art CMOS systolic arrays while being radiation-hard. These results improve the feasibility of using domain wall-based processors, especially for extreme-environment applications such as space.

cond-mat.mes-hall↗