arXiv subjects

Nicolás Wainstein

Publications and source records attributed to Nicolás Wainstein.

6 recordsLinked to original sources

arXiv2026

A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS

The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referred offset trim is the programmed multilevel state of the ferroelectric field-effect transistor (FeFET) that converts the input. Fabricated in 28-nm CMOS, the 6.07-$μ$m$^2$ VTC consists of a current-starved inverter with the FeFET and a parallel NMOS leaker in its tail, a capacitor bank, and a following inverter. The programmed state shifts the transfer curve onto the input range, leaving the gain to the capacitor bank and the leaker bias. Measured at 10~MS/s, centered states weaken the second harmonic from $-$12.5~dB in the low-threshold state to $-$32.2~dB and lower the static integral nonlinearity (INL) at 5~bit from 2.42 to 0.92~LSB. Post-layout simulations indicate that the proposed VTC can operate at 500~MS/s, drawing 2.0~$μ$W from a 0.9-V supply, with nearly unchanged distortion and gain up to 700~MS/s. Across simulated process corners and $\pm$10\,\% supply variation, the input-referred offset is calibrated to within 10~mV and the gain to within 4\,\% of nominal by adjusting the programmed state and leaker bias.

cs.ET↗

arXiv2026

Energy and Scaling Limits of Phase-Change Memory

Phase change memory (PCM) relies on a reversible transition between amorphous and crystalline states of a material, and stands as a promising candidate for next-generation, energy-efficient data storage and neuromorphic hardware. Here, we review key innovations that have driven PCM technology to achieve energy consumption down to only tens of femtojoules per bit, and could further advance it closer to its fundamental limits. Because PCM switching is induced thermally, we highlight improvements in energy-efficiency through two primary strategies: by minimizing the active phase change material region to sub-10 nm dimensions, and by enhancing heat confinement within PCM devices to reduce thermal dissipation into the surrounding environment. While the theoretical limits could reach single attojoules per cubic nanometer of memory material, realizing these limits in practice is significantly constrained by electrical and thermal parasitics, particularly at contacts and interfaces.

cond-mat.mtrl-sci↗

arXiv2026

A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS

Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated and reconfigurable TD-nvIMC macro, fabricated in 28 nm CMOS, that combines a ferroelectric FET (FeFET)-based content-addressable memory array, a cascaded delay element chain, and a time-to-digital converter. The architecture supports binary multiply-and-accumulate (MAC) operations using XOR- and AND-based matching, as well as in-memory Boolean logic and arithmetic functions. Sub-nanosecond MAC resolution is achieved through experimentally demonstrated 550 ps delay steps, representing a 2000$\times$ improvement over prior FeFET TD-nvIMC work, enabled by multilevel-state calibration with $\leq$ 100 ps resolution. Write-disturb resilience is ensured via isolated triple-well bulks. The proposed macro achieves a measured throughput of 222.2 MOPS/cell and energy efficiency of 1887 TOPS/W at 0.85 V, establishing a viable path toward scalable, energy-efficient TD-nvIMC accelerators.

cs.ET↗

arXiv2025

Fast-Locking and High-Resolution Mixed-Mode DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS) locking, designed to cover a broad frequency range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the binary search controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed MM-DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75 V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed MM-DLL achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking FoM of 0.01 $pJ\cdot ns^2$.

cs.AR↗

arXiv2022

Stateful Logic using Phase Change Memory

Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly by resistive RAM (RRAM). Here we present a new method to design stateful logic using a different resistive memory - phase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanism and functionality of PCM compared to RRAM. Since the proposed stateful logic form a functionally complete set, these gates enable sequential execution of any logic function within the memory, paving the way to PCM-based digital processing-in-memory systems.

cs.ET↗

arXiv2021

Uncovering Phase Change Memory Energy Limits by Sub-Nanosecond Probing of Power Dissipation Dynamics

Phase change memory (PCM) is one of the leading candidates for neuromorphic hardware and has recently matured as a storage class memory. Yet, energy and power consumption remain key challenges for this technology because part of the PCM device must be self-heated to its melting temperature during reset. Here, we show that this reset energy can be reduced by nearly two orders of magnitude by minimizing the pulse width. We utilize a high-speed measurement setup to probe the energy consumption in PCM cells with varying pulse width (0.3 to 40 nanoseconds) and uncover the power dissipation dynamics. A key finding is that the switching power (P) remains unchanged for pulses wider than a short thermal time constant of the PCM ($τ$$_t$$_h$ < 1 ns in 50 nm diameter device), resulting in a decrease of energy (E=P$τ$) as the pulse width $τ$ is reduced in that range. In other words, thermal confinement during short pulses is achieved by limiting the heat diffusion time. Our improved programming scheme reduces reset energy density below 0.1 nJ/$μ$m$^2$, over an order of magnitude lower than state-of-the-art PCM, potentially changing the roadmap of future data storage technology and paving the way towards energy-efficient neuromorphic hardware

cond-mat.mes-hall↗