arXiv subjects

Nicolas Delfosse

Publications and source records attributed to Nicolas Delfosse.

At least 19 recordsLinked to original sources

arXiv2026

Computing 256-bit elliptic curve discrete logarithms in 26 days on a fault-tolerant trapped-ion quantum computer with 20,000 qubits

One of the strengths of our recently proposed Walking Cat Architecture for a trapped-ion quantum computer is that it is straightforward to extend and optimize for a specific application. As a proof-of-concept, here we present such optimizations for solving the $256$-bit elliptic curve discrete logarithm problem (ECDLP) on $\mathtt{secp256k1}$, which is the elliptic curve used by blockchain technologies such as Bitcoin, using Shor's algorithm. We optimize the circuits from Schrottenloher's recent work and arrive at a logical quantum circuit for solving the ECDLP using about $1450$ qubits and $40\cdot 10^6$ Toffoli gates, with a rigorous lower bound on the logical-level success probability that holds with confidence at least $1-2^{-128}$. Using our compilation toolchain with manual optimization of the logical layout and integrated routing, we produce estimates for the logical measurement depth and the required number of physical qubits by compiling all components to measurement schedules that obey the architectural constraints. A key ingredient is a fast CCZ magic-state factory and a depth-one CCZ state injection, reducing the execution time of CCZ gates by a factor of $31$. We increase the logical-measurement parallelism using non-overlapping cat-based measurements in parallel, and we leverage the recently proposed logical CliNR protocol to speed up Clifford operations. To reduce the qubit overhead, we introduce a more efficient loss correction protocol, design a layout that allows us to recycle the CliNR ancilla qubits, and provision reusable cat-state resources according to the circuit's peak measurement parallelism. All results and optimizations combined, we conclude that a trapped-ion quantum computer based on our architecture can solve the ECDLP on $\mathtt{secp256k1}$ in approximately 25.7 days using 19,397 physical qubits with an estimated success probability of $63\%$.

quant-ph↗

arXiv2026

Real-time decoder for a MegaQuOp quantum computer using a single CPU

As quantum computers advance toward the regime of MegaQuOp machines executing millions of gates, a decoding system capable of real-time error correction in such a device will be crucial. Recent efforts have been focused on decoding an error-corrected memory or a small number of logical operations. Here we demonstrate an end-to-end real-time decoding stack for a universal fault-tolerant trapped-ion quantum computer architecture capable of decoding real workloads with millions of logical gates over hundreds of logical qubits. The complete pipeline, including on the fly detector error model generation, decoding of all logical qubits, logical operations, and magic-state factories, runs on a single CPU. We benchmark the decoder on practically relevant quantum applications spanning up to 408 logical qubits, and up to one million $T$ gates. Assuming a trapped-ion architecture with 1 to 5 ms cycle time, the decoding delay stretches the computation by less than $0.3\%$ at $p_{\mathrm{CNOT}}=10^{-4}$ and less than $12\%$ at $p_{\mathrm{CNOT}}=5\times 10^{-4}$ for all workloads studied. These results demonstrate real-time decoding at MegaQuOp scale on a single conventional CPU.

quant-ph↗

arXiv2026

Fast logical operations in quantum LDPC codes using simple resource states

Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed-up of up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed-up of up to $5\times$ for Toffoli gates.

quant-ph↗

arXiv2026

Breakeven demonstration of quantum low-density parity-check codes

High-rate quantum low-density parity-check (qLDPC) codes are a leading candidate for fault-tolerant quantum computing. They feature higher encoding rates than planar alternatives such as the surface code, but their implementation often entails significant hardware hurdles like the need for long-range couplers. We leverage the flexibility of a trapped-ion quantum computer to demonstrate nine quantum error-correcting codes with starkly different qubit connectivity requirements on a single device without any hardware reconfiguration. These experiments span three families of quantum error-correcting codes: qLDPC codes, topological codes, and concatenated codes. With a qLDPC code encoding 4 logical qubits into 18 physical qubits, we achieve a logical error rate up to $9\times$ better than a previous demonstration of a similar code on superconducting solid-state qubits. Moreover, our implementation exhibits breakeven performance, with some instances achieving qubit lifetimes comparable to or slightly exceeding that of our trapped-ion qubits. We use a novel implementation of the optical-metastable-ground (OMG) architecture for addressable mid-circuit measurement and reset, which enables us to perform these experiments without any ion transport or dedicated coolant ions, requirements that typically consume a large fraction of the runtime or ion count of trapped-ion quantum computers.

quant-ph↗

arXiv2026

Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture

We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.

quant-ph↗

arXiv2025

Advantage in distributed quantum computing with slow interconnects

The main bottleneck for distributed quantum computing is the rate at which entanglement is produced between quantum processing units (QPUs). In this work, we prove that multiple QPUs connected through slow interconnects can outperform a monolithic architecture made with a single QPU. We consider a distributed quantum computing model with the following assumptions: (1) each QPU is linked to only two other QPUs, (2) each link produces only one Bell pair at a time, (3) the time to generate a Bell pair is $\tau_e$ times longer than the gate time. We propose a distributed version of the CliNR partial error correction scheme respecting these constraints and we show through circuit level simulations that, even if the entanglement generation time $\tau_e$ is up to five times longer than the gate time, distributed CliNR can achieve simultaneously a lower logical error rate and a shorter depth than both the direct implementation and the monolithic CliNR implementation of random Clifford circuits. In the asymptotic regime, we relax assumption (2) and we prove that links producing $O(t/\ln t)$ Bell pairs in parallel, where $t$ is the number of QPUs, is sufficient to avoid stalling distributed CliNR, independently of the number of qubits per QPU. This demonstrates the potential of distributed CliNR for near-term multi-QPU devices. Moreover, we envision a distributed quantum superiority experiment based on the conjugated Clifford circuits of Bouland, Fitzsimons and Koh implemented with distributed CliNR.

quant-ph↗

arXiv2025

Beam search decoder for quantum LDPC codes

We propose a decoder for quantum low density parity check (LDPC) codes based on a beam search heuristic guided by belief propagation (BP). Our beam search decoder applies to all quantum LDPC codes and achieves different speed-accuracy tradeoffs by tuning its parameters such as the beam width. We perform numerical simulations under circuit level noise for the $[[144, 12, 12]]$ bivariate bicycle (BB) code at noise rate $p=10^{-3}$ to estimate the logical error rate and the 99.9 percentile runtime and we compare with the BP-OSD decoder which has been the default quantum LDPC decoder for the past six years. A variant of our beam search decoder with a beam width of 64 achieves a $17\times$ reduction in logical error rate. With a beam width of 8, we reach the same logical error rate as BP-OSD with a $26.2\times$ reduction in the 99.9 percentile runtime. We identify the beam search decoder with beam width of 32 as a promising candidate for trapped ion architectures because it achieves a $5.6\times$ reduction in logical error rate with a 99.9 percentile runtime per syndrome extraction round below 1ms at $p=5 \times10^{-4}$. Remarkably, this is achieved in software on a single core, without any parallelization or specialized hardware (FPGA, ASIC), suggesting one might only need three 32-core CPUs to decode a trapped ion quantum computer with 1000 logical qubits.

quant-ph↗

arXiv2025

Recursive Clifford noise reduction

Clifford noise reduction (CliNR) is a partial error correction scheme that reduces the logical error rate of Clifford circuits at the cost of a modest qubit and gate overhead. The CliNR implementation of an $n$-qubit Clifford circuit of size $s$ achieves a vanishing logical error rate if $snp^2\rightarrow 0$ where $p$ is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When $np \rightarrow 0$, the logical error rate can be vanishingly small. This implementation requires $\left(2\left\lceil \log(sp)\right\rceil+3\right)n+1$ qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.

quant-ph↗

arXiv2025

Correction of chain losses in trapped ion quantum computers

Neutral atom quantum computers and to a lesser extent trapped ions may suffer from atom loss. In this work, we investigate the impact of atom loss in long chains of trapped ions. Even though this is a relatively rare event, ion loss in long chains must be addressed because it destabilizes the entire chain resulting in the loss of all the qubits of the chain. We propose a solution to the chain loss problem based on (1) a quantum error correction code distributed over multiple long chains, (2) beacon qubits within each long chain to detect the loss of a chain, and (3) a decoder adapted to correct a combination of circuit faults and erasures after beacon qubits convert chain losses into erasures. We verify the chain loss correction capability of our scheme through circuit level simulations with a distributed $[[72,12,6]]$ BB code with beacon qubits.

quant-ph↗

arXiv2025

Cyclic Hypergraph Product Code

Hypergraph product (HGP) codes are one of the most popular family of quantum low-density parity-check (LDPC) codes. Circuit-level simulations show that they can achieve the same logical error rate as surface codes with a reduced qubit overhead. They have been extensively optimized by importing classical techniques such as the progressive edge growth, or through random search, simulated annealing or reinforcement learning techniques. In this work, instead of machine learning (ML) algorithms that improve the code performance through local transformations, we impose additional global symmetries, that are hard to discover through ML, and we perform an exhaustive search. Precisely, we focus on the hypergraph product of two cyclic codes, which we call CxC codes and we study C2 codes which are the product a cyclic code with itself and CxR codes which are the product of a cyclic codes with a repetition code. We discover C2 codes and CxR codes that significantly outperform previously optimized HGP codes, achieving better parameters and a logical error rate per logical qubit that is up to three orders of magnitude better. Moreover, some C2 codes achieve simultaneously a lower logical error rate and a smaller qubit overhead than state-of-the-art LDPC codes such as the bivariate bicycle codes, at the price of a larger block length. Finally, leveraging the cyclic symmetry imposed on the codes, we design an efficient planar layout for the QCCD architecture, allowing for a trapped ion implementation of the syndrome extraction circuit in constant depth.

quant-ph↗

arXiv2025

Distributed fault-tolerant quantum memories over a 2xL array of qubit modules

We propose an architecture for a quantum memory distributed over a $2 \times L$ array of modules equipped with a cyclic shift implemented via flying qubits. The logical information is distributed across the first row of $L$ modules and quantum error correction is executed using ancilla modules on the second row equipped with a cyclic shift. This work proves that quantum LDPC codes such as BB codes can maintain their performance in a distributed setting while using solely one simple connector: a cyclic shift. We propose two strategies to perform quantum error correction on a $2 \times L$ module array: (i) The cyclic layout which applies to any stabilizer codes, whereas previous results for qubit arrays are limited to CSS codes. (ii) The sparse cyclic layout, specific to bivariate bicycle (BB) codes. For the $[[144,12,12]]$ BB code, using the sparse cyclic layout we obtain a quantum memory with $12$ logical qubits distributed over $12$ modules, containing $12$ physical qubits each. We propose physical implementations of this architecture using flying qubits, that can be faithfully transported, and include qubits encoded in ions, neutral atoms, electrons or photons. We performed numerical simulations when modules are long ion chains and when modules are single-qubit arrays of ions showing that the distributed BB code achieves a logical error rate below $2 \cdot 10^{-6}$ when the physical error rate is $10^{-3}$.

quant-ph↗

arXiv2025

Optimized Clifford Noise Reduction: Theory, Simulations and Experiments

We propose several optimizations of the CliNR partial error correction scheme which implements Clifford circuits by consuming a resource state. Errors are corrected by measuring a sequence of Pauli operators that we refer to as the verification sequence. We first propose a global optimization algorithm searching for a verification sequence resulting in a low logical error rate using tabu search. Then, we introduce a proxy for the logical error rate which is easier to evaluate and we design a two-step optimization algorithm. First, a verification sequence minimizing the proxy is computed, then this sequence is refined by reintroducing the logical error rate. Finally, we identify a large group of automorphisms of the search space which preserve the proxy and we use this symmetry to reduce the size of the search space. This results in a 168 $\times$ (respectively 20,160 $\times$) reduction of the size of the search space for the optimization of verification sequences with three (respectively four) Pauli operators. Our numerical simulations for 20-qubit Clifford circuits with size 400 under the ion chain model show that our optimization algorithms improve the performance of CliNR by 25% and that the two-step optimization achieves the same results as the global optimization with 64% fewer evaluations of the logical error rate. Finally, we perform experiments on a 36-qubit trapped ion quantum computer, without mid-circuit measurements, showing that the CZNR variant of CliNR is at breakeven.

quant-ph↗

arXiv2025

Quantum error correction for long chains of trapped ions

We propose a model for quantum computing with long chains of trapped ions and we design quantum error correction schemes for this model. The main components of a quantum error correction scheme are the quantum code and a quantum circuit called the syndrome extraction circuit, which is executed to perform error correction with this code. In this work, we design syndrome extraction circuits tailored to our ion chain model, a syndrome extraction tuning protocol to optimize these circuits, and we construct new quantum codes that outperform the state-of-the-art for chains of about $50$ qubits. To establish a baseline under the ion chain model, we simulate the performance of surface codes and bivariate bicycle (BB) codes equipped with our optimized syndrome extraction circuits. Then, we propose a new variant of BB codes defined by weight-five measurements, that we refer to as BB5 codes and we identify BB5 codes that achieve a better minimum distance than any BB codes with the same number of logical qubits and data qubits, such as a $[[48, 4, 7]]$ BB5 code. For a physical error rate of $10^{-3}$, the $[[48, 4, 7]]$ BB5 code achieves a logical error rate per logical qubit of $5 \cdot 10^{-5}$, which is four times smaller than the best BB code in our baseline family. It also achieves the same logical error rate per logical qubit as the distance-7 surface code but using four times fewer physical qubits per logical qubit.

quant-ph↗

arXiv2025

Optimizing hypergraph product codes with random walks, simulated annealing and reinforcement learning

Hypergraph products are quantum low-density parity-check (LDPC) codes constructed from two classical LDPC codes. Although their dimension and distance depend only on the parameters of the underlying classical codes, optimizing their performance against various noise channels remains challenging. This difficulty partly stems from the complexity of decoding in the quantum setting. The standard, ad hoc approach typically involves selecting classical LDPC codes with large girth. In this work, we focus on optimizing performance against the quantum erasure channel. A key advantage of this channel is the existence of an efficient maximum-likelihood decoder, which enables us to employ optimization techniques based on sampling random codes, such as Reinforcement Learning (RL) and Simulated Annealing (SA). Our results indicate that these techniques improve performance relative to the state-of-the-art.

quant-ph↗

arXiv2024

Correction of circuit faults in a stacked quantum memory using rank-metric codes

We introduce a model for a stacked quantum memory made with multi-qubit cells, inspired by multi-level flash cells in classical solid-state drive, and we design quantum error correction codes for this model by generalizing rank-metric codes to the quantum setting. Rank-metric codes are used to correct faulty links in classical communication networks. We propose a quantum generalization of Gabidulin codes, which is one of the most popular family of rank-metric codes, and we design a protocol to correct faults in Clifford circuits applied to a stacked quantum memory based on these codes. We envision potential applications to the optimization of stabilizer states and magic states factories, and to variational quantum algorithms. Further work is needed to make this protocol practical. It requires a hardware platform capable of hosting multi-qubit cells with low crosstalk between cells, a fault-tolerant syndrome extraction circuit for rank-metric codes and an associated efficient decoder.

quant-ph↗

arXiv2024

Low-cost noise reduction for Clifford circuits

We propose a Clifford noise reduction (CliNR) scheme that provides a reduction of the logical error rate of Clifford circuit with lower overhead than error correction and without the exponential sampling overhead of error mitigation. CliNR implements Clifford circuits by splitting them into sub-circuits that are performed using gate teleportation. A few random stabilizer measurements are used to detect errors in the resources states consumed by the gate teleportation. This can be seen as a teleported version of the CPC scheme, with offline fault-detection making it scalable. We prove that CliNR achieves a vanishing logical error rate for families of $n$-qubit Clifford circuits with size $s$ such that $nsp^2$ goes to 0, where $p$ is the physical error rate, meaning that it reaches the regime $ns = o(1/p^2)$ whereas the direct implementation is limited to $s = o(1/p)$. Moreover, CliNR uses only $3n+1$ qubits, $2s + o(s)$ gates and has zero rejection rate. This small overhead makes it more practical than quantum error correction in the near term and our numerical simulations show that CliNR provides a reduction of the logical error rate in relevant noise regimes.

quant-ph↗

arXiv2023

How to choose a decoder for a fault-tolerant quantum computer? The speed vs accuracy trade-off

Achieving practical quantum advantage requires a classical decoding algorithm to identify and correct faults during computation. This classical decoding algorithm must deliver both accuracy and speed, but in what combination? When is a decoder "fast enough" or "accurate enough"? In the case of surface codes, tens of decoding algorithms have been proposed, with different accuracies and speeds. However, it has been unclear how to choose the best decoder for a given quantum architecture. Should a faster decoder be used at the price of reduced accuracy? Or should a decoder sacrifice accuracy to fit within a given time constraint? If a decoder is too slow, it may be stopped upon reaching a time bound, at the price of some time-out failures and an increased failure rate. What then is the optimal stopping time of the decoder? By analyzing the speed vs. accuracy tradeoff, we propose strategies to select the optimal stopping time for a decoder for different tasks. We design a protocol to select the decoder that minimizes the spacetime cost per logical gate, for logical computation of a given depth. Our protocol enables comparison of different decoders, and the selection of an appropriate decoder for a given fault-tolerant quantum computing architecture. We illustrate our protocol for the surface code equipped with a desktop implementation of the PyMatching decoder. We estimate PyMatching is fast enough to implement thousands of logical gates with a better accuracy than physical qubits. However, we find it is not sufficiently fast to reach 10^5 logical gates, under certain assumptions, due to the decoding delay which forces qubits to idle and accumulate errors while idling. We expect further improvements to PyMatching are possible by running it on a better machine or by reducing the OS interference.

quant-ph↗

arXiv2023

Simulation of noisy Clifford circuits without fault propagation

The design and optimization of a large-scale fault-tolerant quantum computer architecture relies extensively on numerical simulations to assess the performance of each component of the architecture. The simulation of fault-tolerant gadgets, which are typically implemented by Clifford circuits, is done by sampling circuit faults and propagating them through the circuit to check that they do not corrupt the logical data. One may have to repeat this fault propagation trillions of times to extract an accurate estimate of the performance of a fault-tolerant gadget. For some specific circuits, such as the standard syndrome extraction circuit for surface codes, we can exploit the natural graph structure of the set of faults to perform a simulation without fault propagation. We propose a simulation algorithm for all Clifford circuits that does not require fault propagation and instead exploits the mathematical structure of the spacetime code of the circuit. Our algorithm, which we name adjoint-based code (ABC) simulation, relies on the fact that propagation forward is the adjoint of propagation backward in the sense of Proposition 3 from [14]. We use this result to replace the propagation of trillions of fault-configurations by the backward propagation of a small number of Pauli operators which can be precomputed once and for all.

quant-ph↗