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Nikil Dutt

Publications and source records attributed to Nikil Dutt.

58 records · Page 4Linked to original sources

Visual response properties of MSTd emerge from a sparse population code

Neurons in the dorsal subregion of the medial superior temporal (MSTd) area respond to large, complex patterns of retinal flow, implying a role in the analysis of self-motion. Some neurons are selective for the expanding radial motion that occurs as an observer moves through the environment ("heading"), and computational models can account for this finding. However, ample evidence suggests that MSTd neurons may exhibit a continuum of visual response selectivity to large-field motion stimuli, but the underlying computational principles by which these response properties are derived remain poorly understood. Here we describe a computational model of MSTd based on the hypothesis that neurons in MSTd efficiently encode the continuum of large-field retinal flow patterns on the basis of inputs received from neurons in MT, with receptive fields that resemble basis vectors recovered with nonnegative matrix factorization (NMF). These assumptions are sufficient to quantitatively simulate neurophysiological response properties of MSTd cells such as radial, circular, and spiral motion tuning, suggesting that these properties might simply be a by-product of MSTd neurons performing dimensionality reduction on their inputs. At the population level, model MSTd accurately predicts heading using a sparse distributed code, consistent with the idea that biological MSTd might operate in a sparseness regime well-suited to efficiently encode a number of self-motion variables. The present work provides an alternative to the template-model view of MSTd, and offers a biologically plausible account of the receptive field structure across a wide range of visual response properties in MSTd.

q-bio.NC↗

FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations

In today's embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the use of scratch pad memories, with many based on static analysis of a program. However, often it is not possible to perform static analysis and optimization of a program's memory access behavior unless the program is specifically written for this purpose. In this paper we introduce the FORAY model of a program that permits aggressive analysis of the application's memory behavior that further enables such optimizations since it consists of 'for' loops and array accesses which are easily analyzable. We present FORAY-GEN: an automated profile-based approach for extraction of the FORAY model from the original program. We also demonstrate how FORAY-GEN enhances applicability of other memory subsystem optimization approaches, resulting in an average of two times increase in the number of memory references that can be analyzed by existing static approaches.

cs.PL↗

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement

Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.

cs.AR↗

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.

cs.AR↗