Nilesh Shah | Searcharxiv

arXiv2024

Streamlining CXL Adoption for Hyperscale Efficiency

In our exploration of Composable Memory systems utilizing CXL, we focus on overcoming adoption barriers at Hyperscale, underscored by economic models demonstrating Total Cost of Ownership (TCO). While CXL addresses the pressing memory capacity needs of emerging Hyperscale applications, the escalating demands from evolving use cases such as AI outpace the capabilities of current CXL solutions. Hyperscalers resort to software-based memory (de)compression technology, alleviating memory capacity, storage, and network constraints but incurring a notable "Tax" on Compute CPU cycles. As a pivotal guide to the CXL community, Hyperscalers have formulated the groundbreaking Open Compute Project (OCP) Hyperscale CXL Tiered Memory Expander specification. If implemented, this specification lowers TCO adoption barriers, enabling diverse CXL deployments at both Hyperscaler and Enterprise levels. We present a CXL integrated solution, aligning with the aforementioned specification, introducing an energy-efficient, scalable, hardware-accelerated, Lossless Compressed Memory CXL Tier. This solution, slated for mid-2024 production and open for integration with Memory Expander controller manufacturers, offers 2-3X CXL memory compression in nanoseconds, delivering a 20-25% reduction in TCO for end customers without requiring additional physical slots. In our discussion, we pinpoint areas for collaborative innovation within the CXL Community to expedite software/hardware advancements for CXL Tiered Memory Expansion. Furthermore, we delve into unresolved challenges in Pooled deployment and explore potential solutions, collectively aiming to make CXL adoption a "No Brainer" at Hyperscale.

cs.ET↗

arXiv2021

Multi-center validation study of automated classification of pathological slowing in adult scalp electroencephalograms via frequency features

Pathological slowing in the electroencephalogram (EEG) is widely investigated for the diagnosis of neurological disorders. Currently, the gold standard for slowing detection is the visual inspection of the EEG by experts, which is time-consuming and subjective. To address those issues, we propose three automated approaches to detect slowing in EEG: Threshold-based Detecting System (TDS), Shallow Learning-based Detecting System (SLDS), and Deep Learning-based Detecting System (DLDS). These systems are evaluated on channel-, segment- and EEG-level. The TDS, SLDS, and DLDS performs prediction via detecting slowing at individual channels, and those detections are arranged in histograms for detection of slowing at the segment- and EEG-level. We evaluate the systems through Leave-One-Subject-Out (LOSO) cross-validation (CV) and Leave-One-Institution-Out (LOIO) CV on four datasets from the US, Singapore, and India. The DLDS achieved the best overall results: LOIO CV mean balanced accuracy (BAC) of 71.9%, 75.5%, and 82.0% at channel-, segment- and EEG-level, and LOSO CV mean BAC of 73.6%, 77.2%, and 81.8% at channel-, segment-, and EEG-level. The channel- and segment-level performance is comparable to the intra-rater agreement (IRA) of an expert of 72.4% and 82%. The DLDS can process a 30-minutes EEG in 4 seconds and can be deployed to assist clinicians in interpreting EEGs.

eess.SP↗