arXiv subjects

Nils Pohl

Publications and source records attributed to Nils Pohl.

3 recordsLinked to original sources

arXiv2026

Multistatic J-Band Radar TX/RX Chipset in SiGe BiCMOS with Integrated x16 Frequency Multiplier Chain and High EIRP

This work presents the design and measurement of a multistatic J-band radar chipset comprising a transmitter and a receiver MMIC both featuring an integrated $times$16 frequency multiplier chain for low-frequency local-oscillator distribution and scalable radar configurations. Multistatic radar architectures can sustain high transmission power and high receiver sensitivity simultaneously an advantage that is fully leveraged in the present chipset. To this end a four-way power-combining amplifier chain integrated on the transmitter MMIC delivers an output power of 11.2 dBm. The resulting measured EIRP is 41 dBm at 292 GHz with a collimating PTFE lens and 8.8 dBm without a lens. Despite the high frequency-multiplication factor an on-chip harmonic rejection better than 24 dBc was measured while a radiated in-band harmonic rejection of approximately 50 dBc was achieved through multiple filter stages. The receiver MMIC incorporates a three-stage low-noise amplifier and exhibits an overall conversion gain of 43.3 dB at 292 GHz. Integrated on-chip patch antennas facilitate system integration and the use of highly directive dielectric lenses making the chipset suitable for long-range radar measurements which are demonstrated up to 150 m. The MMICs are realized in a 130 nm SiGe BiCMOS technology with an f_T and f_max of 500 GHz and 610 GHz respectively.

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arXiv2021

ClepsydraCache -- Preventing Cache Attacks with Time-Based Evictions

In the recent past, we have witnessed the shift towards attacks on the microarchitectural CPU level. In particular, cache side-channels play a predominant role as they allow an attacker to exfiltrate secret information by exploiting the CPU microarchitecture. These subtle attacks exploit the architectural visibility of conflicting cache addresses. In this paper, we present ClepsydraCache, which mitigates state-of-the-art cache attacks using a novel combination of cache decay and index randomization. Each cache entry is linked with a Time-To-Live (TTL) value. We propose a new dynamic scheduling mechanism of the TTL which plays a fundamental role in preventing those attacks while maintaining performance. ClepsydraCache efficiently protects against the latest cache attacks such as Prime+(Prune+)Probe. We present a full prototype in gem5 and lay out a proof-of-concept hardware design of the TTL mechanism, which demonstrates the feasibility of deploying ClepsydraCache in real-world systems.

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arXiv2020

Real-Time Radar-Based Gesture Detection and Recognition Built in an Edge-Computing Platform

In this paper, a real-time signal processing frame-work based on a 60 GHz frequency-modulated continuous wave (FMCW) radar system to recognize gestures is proposed. In order to improve the robustness of the radar-based gesture recognition system, the proposed framework extracts a comprehensive hand profile, including range, Doppler, azimuth and elevation, over multiple measurement-cycles and encodes them into a feature cube. Rather than feeding the range-Doppler spectrum sequence into a deep convolutional neural network (CNN) connected with recurrent neural networks, the proposed framework takes the aforementioned feature cube as input of a shallow CNN for gesture recognition to reduce the computational complexity. In addition, we develop a hand activity detection (HAD) algorithm to automatize the detection of gestures in real-time case. The proposed HAD can capture the time-stamp at which a gesture finishes and feeds the hand profile of all the relevant measurement-cycles before this time-stamp into the CNN with low latency. Since the proposed framework is able to detect and classify gestures at limited computational cost, it could be deployed in an edge-computing platform for real-time applications, whose performance is notedly inferior to a state-of-the-art personal computer. The experimental results show that the proposed framework has the capability of classifying 12 gestures in real-time with a high F1-score.

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