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Nimish Shah

Publications and source records attributed to Nimish Shah.

At least 19 recordsLinked to original sources
arXiv2026

AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing

Probabilistic graphical models (PMs) are popular to empower machine learning with the ability of reasoning and decision-making. To perform approximate inference in PMs, sampling-based Markov Chain Monte Carlo (MCMC) algorithms are commonly employed. Unfortunately, MCMC is compute-intensive and hard to run in parallel, resulting in inefficient execution on modern CPU/GPU platforms. This paper proposes \name{}, an Approximate Inference Accelerator designed to empower decision-making and reasoning at the edge. \name{} consists of a RISC-V host, and a 2D mesh of 16 customized RISC-V cores optimized to efficiently support PM inference, each featuring (i) a novel non-normalized Knuth-Yao sampler and interpolation unit; and (ii) core-to-core direct data access via the register file, which provides solutions for compute-intensive operations. To fully exploit the parallel potential of Markov Chain Monte Carlo (MCMC) algorithms, a customized compiler chain has been developed for effective spatial mapping and scheduling on the chip. \name{} can generate 1277 MSample/s at 0.9V and 20 GSamples/s/W at 0.7V which is up to 2$\times$ faster and 1.45x more energy efficient compared to the previous state-of-the-art Markov Random Field (MRF) accelerator. We further map Bayesian Networks benchmark onto \name{} to show the flexibility of our design.

cs.AR↗
arXiv2026

AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm

Probabilistic models (PMs) are essential in advancing machine learning capabilities, particularly in safety-critical applications involving reasoning and decision-making. Among the methods employed for inference in these models, sampling-based Markov Chain Monte Carlo (MCMC) techniques are widely used. However, MCMC methods come with significant computational costs and are inherently challenging to parallelize, resulting in inefficient execution on conventional CPU/GPU platforms. To overcome these challenges, this paper presents AIA, a multi-core RISC-V System-on-Chip (SoC) design fabricated using Intel's 16 nm process technology. Our Approximate Inference Accelerator (AIA) is specifically designed to empower edge devices with robust decision-making and reasoning abilities. The AIA architecture incorporates a RISC-V host processor to manage chip-to-chip data communication and a 2D mesh of 16 custom versatile RISC-V cores optimized for high-efficiency approximate inference. Each core features (i) custom instructions and datapath blocks for non-normalized Knuth-Yao (KY) sampling, as well as for the interpolation of non-linear functions (e.g., logarithmic, exponential), and (ii) direct data access to the register file of each neighboring core, to reduce the data movement costs of frequent data exchanges between nearby cores. To further capitalize on the parallelism potential in MCMC algorithms, we developed a specialized compile chain that enables efficient spatial mapping and scheduling across the cores.

cs.AR↗
arXiv2026

aiPlato: A Novel AI Tutoring and Step-wise Feedback System for Physics Homework

This exploratory study examines the classroom deployment of aiPlato, an AI-enabled homework platform, in a large introductory physics course at the University of Texas at Arlington. Designed to support open-ended problem solving, aiPlato provides step-wise feedback and iterative guidance through tools such as "Evaluate My Work" and "AI Tutor Chat", while preserving opportunities for productive struggle. Over four optional extra-credit assignments, the platform captured detailed student interaction data, which were analyzed alongside course performance and end-of-semester survey responses. We examine how students engaged with different feedback tools, whether engagement patterns were associated with performance on the cumulative final exam, and how students perceived the platform's usability and learning value. Students who engaged more frequently with aiPlato tended to achieve higher final exam scores, with a mean difference corresponding to a standardized effect size of approximately 0.81 between high and low engagement groups after controlling for prior academic performance. Usage patterns and survey responses indicate that students primarily relied on iterative, formative feedback rather than solution-revealing assistance. As a quasi-experimental pilot study, these findings do not establish causality and may reflect self-selection effects. Nonetheless, the results demonstrate the feasibility of integrating AI-mediated, step-wise feedback into authentic physics homework and motivate future controlled studies of AI-assisted tutoring systems.

physics.ed-ph↗
arXiv2025

Decoupled Control Flow and Data Access in RISC-V GPGPUs

Vortex, a newly proposed open-source GPGPU platform based on the RISC-V ISA, offers a valid alternative for GPGPU research over the broadly-used modeling platforms based on commercial GPUs. Similarly to the push originating from the RISC-V movement for CPUs, Vortex can enable a myriad of fresh research directions for GPUs. However, as a young hardware platform, it currently lacks the performance competitiveness of commercial GPUs, which is crucial for widespread adoption. State-of-the-art GPUs, in fact, rely on complex architectural features, still unavailable in Vortex, to hide the micro-code overheads linked to control flow (CF) management and memory orchestration for data access. In particular, these components account for the majority of the dynamic instruction count in regular, memory-intensive kernels, such as linear algebra routines, which form the basis of many applications, including Machine Learning. To address these challenges with simple yet powerful micro-architecture modifications, this paper introduces decoupled CF and data access through 1.) a hardware CF manager to accelerate branching and predication in regular loop execution and 2.) decoupled memory streaming lanes to further hide memory latency with useful computation. The evaluation results for different kernels show 8$\times$ faster execution, 10$\times$ reduction in dynamic instruction count, and overall performance improvement from 0.35 to 1.63 $\mathrm{GFLOP/s/mm^2}$. Thanks to these enhancements, Vortex can become an ideal playground to enable GPGPU research for the next generation of Machine Learning.

cs.AR↗
arXiv2024

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis

GPGPU execution analysis has always been tied to closed-source, proprietary benchmarking tools that provide high-level, non-exhaustive, and/or statistical information, preventing a thorough understanding of bottlenecks and optimization possibilities. Open-source hardware platforms offer opportunities to overcome such limits and co-optimize the full {hardware-mapping-algorithm} compute stack. Yet, so far, this has remained under-explored. In this work, we exploit micro-architecture parameter analysis to develop a hardware-aware, runtime mapping technique for OpenCL kernels on the open Vortex RISC-V GPGPU. Our method is based on trace observations and targets optimal hardware resource utilization to achieve superior performance and flexibility compared to hardware-agnostic mapping approaches. The technique was validated on different architectural GPU configurations across several OpenCL kernels. Overall, our approach significantly enhances the performance of the open-source Vortex GPGPU, contributing to unlocking its potential and usability.

cs.AR↗
arXiv2022

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

A growing number of applications like probabilistic machine learning, sparse linear algebra, robotic navigation, etc., exhibit irregular data flow computation that can be modeled with directed acyclic graphs (DAGs). The irregularity arises from the seemingly random connections of nodes, which makes the DAG structure unsuitable for vectorization on CPU or GPU. Moreover, the nodes usually represent a small number of arithmetic operations that cannot amortize the overhead of launching tasks/kernels for each node, further posing challenges for parallel execution. To enable energy-efficient execution, this work proposes DAG processing unit (DPU) version 2, a specialized processor architecture optimized for irregular DAGs with static connectivity. It consists of a tree-structured datapath for efficient data reuse, a customized banked register file, and interconnects tuned to support irregular register accesses. DPU-v2 is utilized effectively through a targeted compiler that systematically maps operations to the datapath, minimizes register bank conflicts, and avoids pipeline hazards. Finally, a design space exploration identifies the optimal architecture configuration that minimizes the energy-delay product. This hardware-software co-optimization approach results in a speedup of 1.4$\times$, 3.5$\times$, and 14$\times$ over a state-of-the-art DAG processor ASIP, a CPU, and a GPU, respectively, while also achieving a lower energy-delay product. In this way, this work takes an important step toward enabling an embedded execution of emerging DAG workloads.

cs.AR↗
arXiv2022

GRAPHOPT: constrained-optimization-based parallelization of irregular graphs

Sparse, irregular graphs show up in various applications like linear algebra, machine learning, engineering simulations, robotic control, etc. These graphs have a high degree of parallelism, but their execution on parallel threads of modern platforms remains challenging due to the irregular data dependencies. The execution performance can be improved by efficiently partitioning the graphs such that the communication and thread synchronization overheads are minimized without hurting the utilization of the threads. To achieve this, this paper proposes GRAPHOPT, a tool that models the graph parallelization as a constrained optimization problem and uses the open Google OR-Tools solver to find good partitions. Several scalability techniques are developed to handle large real-world graphs with millions of nodes and edges. Extensive experiments are performed on the graphs of sparse matrix triangular solves (linear algebra) and sum-product networks (machine learning), respectively, showing a mean speedup of 2.0X and 1.8X over previous state-of-the-art libraries, demonstrating the effectiveness of the constrained-optimization-based graph parallelization.

cs.DC↗
arXiv2021

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm

Computation in several real-world applications like probabilistic machine learning, sparse linear algebra, and robotic navigation, can be modeled as irregular directed acyclic graphs (DAGs). The irregular data dependencies in DAGs pose challenges to parallel execution on general-purpose CPUs and GPUs, resulting in severe under-utilization of the hardware. This paper proposes DPU, a specialized processor designed for the efficient execution of irregular DAGs. The DPU is equipped with parallel compute units that execute different subgraphs of a DAG independently. The compute units can synchronize within a cycle using a hardware-supported synchronization primitive, and communicate via an efficient interconnect to a global banked scratchpad. Furthermore, a precision-scalable posit arithmetic unit is developed to enable application-dependent precision. The DPU is taped-out in 28nm CMOS, achieving a speedup of 5.1$\times$ and 20.6$\times$ over state-of-the-art CPU and GPU implementations on DAGs of sparse linear algebra and probabilistic machine learning workloads. This performance is achieved while operating at a power budget of 0.23W, as opposed to 55W and 98W of the CPU and GPU, resulting in a peak efficiency of 538 GOPS/W with DPU, which is 1350$\times$ and 9000$\times$ higher than the CPU and GPU, respectively. Thus, with specialized architecture, DPU enables low-power execution of irregular DAG workloads.

cs.AR↗
arXiv2021

ProbLP: A framework for low-precision probabilistic inference

Bayesian reasoning is a powerful mechanism for probabilistic inference in smart edge-devices. During such inferences, a low-precision arithmetic representation can enable improved energy efficiency. However, its impact on inference accuracy is not yet understood. Furthermore, general-purpose hardware does not natively support low-precision representation. To address this, we propose ProbLP, a framework that automates the analysis and design of low-precision probabilistic inference hardware. It automatically chooses an appropriate energy-efficient representation based on worst-case error-bounds and hardware energy-models. It generates custom hardware for the resulting inference network exploiting parallelism, pipelining and low-precision operation. The framework is validated on several embedded-sensing benchmarks.

cs.AR↗
arXiv2021

Acceleration of probabilistic reasoning through custom processor architecture

Probabilistic reasoning is an essential tool for robust decision-making systems because of its ability to explicitly handle real-world uncertainty, constraints and causal relations. Consequently, researchers are developing hybrid models by combining Deep Learning with probabilistic reasoning for safety-critical applications like self-driving vehicles, autonomous drones, etc. However, probabilistic reasoning kernels do not execute efficiently on CPUs or GPUs. This paper, therefore, proposes a custom programmable processor to accelerate sum-product networks, an important probabilistic reasoning execution kernel. The processor has an optimized datapath architecture and memory hierarchy optimized for sum-product networks execution. Experimental results show that the processor, while requiring fewer computational and memory units, achieves a 12x throughput benefit over the Nvidia Jetson TX2 embedded GPU platform.

cs.AR↗
arXiv2019

Primitive rational points on expanding horocycles in products of the modular surface with the torus

We prove effective equidistribution of primitive rational points and of primitive rational points defined by monomials along long horocycle orbits in products of the torus and the modular surface. This answers a question posed in joint work by the first and the last named author with Shahar Mozes and Uri Shapira. Under certain congruence conditions we prove the joint equidistribution of conjugate rational points in the two-torus and the modular surface.

math.DS↗
arXiv2019

Quantitative behavior of unipotent flows and an effective avoidance principle

We give an effective bound on how much time orbits of a unipotent group $U$ on an arithmetic quotient $G/\Gamma$ can stay near homogeneous subvarieties of $G /\Gamma$ corresponding to $\mathbb Q$-subgroups of $G$. In particular, we show that if such a $U$-orbit is moderately near a proper homogeneous subvariety of $G/\Gamma$ for a long time it is very near a different homogeneous subvariety. Our work builds upon the linearization method of Dani and Margulis. Our motivation in developing these bounds is in order to prove quantitative density statements about unipotent orbits, which we plan to pursue in a subsequent paper. New qualitative implications of our effective bounds are also given.

math.DS↗
arXiv2018

Equidistribution of dilated curves on nilmanifolds

Generalizing classic results for a family of measures in the torus, for a family $(μ_t)_{t\geq 0}$ of measures defined on a nilmanifold $X$, we study conditions under which the family equidistributes, meaning conditions under which the measures $μ_t$ converge as $t\to\infty$ in the weak$^\ast$ topology to the Haar measure on $X$. We give general conditions on a family of measures defined by a dilation process, showing necessary and sufficient conditions for equidistribution as the family dilates, along with conditions such that this holds for all dilates outside some set of density zero. Furthermore, we show that these two types of equidistribution are different.

math.DS↗
arXiv2016

Equidistribution of curves in homogeneous spaces and Dirichlet's approximation theorem for matrices

In this paper, we study an analytic curve $φ: I=[a,b]\rightarrow \mathrm{M}(m\times n, \mathbb{R})$ in the space of $m$ by $n$ real matrices, and show that if $φ$ satisfies certain geometric condition, then for almost every point on the curve, the Diophantine approximation given by Dirichlet's Theorem can not be improved. To do this, we embed the curve into some homogeneous space $G/Γ$, and prove that under the action of some expanding diagonal subgroup $A= \{a(t): t \in \mathbb{R}\}$, the translates of the curve tend to be equidistributed in $G/Γ$, as $t \rightarrow +\infty$.

math.DS↗
arXiv2015

Equidistribution of primitive rational points on expanding horospheres

We confirm a conjecture of Jens Marklof regarding the equidistribution of certain sparse collections of points on expanding horospheres. These collections are obtained by intersecting the expanded horosphere with a certain manifold of complementary dimension and turns out to be of arithmetic nature. This equidistribution result is then used along the lines suggested by Marklof to give an analogue of a result of W. Schmidt regarding the distribution of shapes of lattices orthogonal to integer vectors.

math.DS↗
arXiv2012

Equidistribution and Counting for orbits of geometrically finite hyperbolic groups

Let G be the identity component of SO(n,1), acting linearly on a finite dimensional real vector space V. Consider a vector w_0 in V such that the stabilizer of w_0 is a symmetric subgroup of G or the stabilizer of the line Rw_0 is a parabolic subgroup of G. For any non-elementary discrete subgroup Gamma of G with w_0Gamma discrete, we compute an asymptotic formula for the number of points in w_0Gamma of norm at most T, provided that the Bowen-Margulis-Sullivan measure on the associated hyperbolic manifold and the Gamma skinning size of w_0 are finite. The main ergodic ingredient in our approach is the description for the limiting distribution of the orthogonal translates of a totally geodesically immersed closed submanifold of Gamma\H^n. We also give a criterion on the finiteness of the Gamma skinning size of w_0 for Gamma geometrically finite.

math.DS↗
arXiv2011

Limits of translates of divergent geodesics and Integral points on one-sheeted hyperboloids

For any non-uniform lattice $Γ$ in $SL(2,R)$, we describe the limit distribution of orthogonal translates of a divergent geodesic in $Γ\backslash SL(2,R)$. As an application, for a quadratic form $Q$ of signature $(2,1)$, a lattice $Γ$ in its isometry group, and $v_0\in R^3$ with $Q(v_0)>0$, we compute the asymptotic (with a logarithmic error term) of the number of points in a discrete orbit $v_0Γ$ of norm at most $T$, when the stabilizer of $v_0$ in $Γ$ is finite. Our result in particular implies that for any non-zero integer $d$, the smoothed count for number of integral binary quadratic forms with discriminant $d^2$ and with coefficients bounded by $T$ is asymptotic to $c\cdot T \log T +O(T)$.

math.NT↗