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Nithil Harris Manimaran

Publications and source records attributed to Nithil Harris Manimaran.

3 recordsLinked to original sources

Leveraging Non-Equilibrium ECRAM Dynamics for Short-Term Plasticity in Neuromorphic Circuits

Short-term plasticity (STP) is fundamental to temporal information processing in biological neural systems but remains difficult to realize efficiently in neuromorphic hardware. Memristive electrochemical random-access memory (ECRAM) devices naturally exhibit non-equilibrium ionic dynamics that produce transient conductance modulation; however, these behaviors are typically treated as undesirable variability or tolerated as side effects in memory-centric computing paradigms. In this work, we instead transform these volatile dynamics from a tolerated device artifact into a computational resource through a cross-layer device-circuit-system co-design framework. We introduce a delay-feedback leaky integrate-and-fire (LIF) neuron architecture co-designed with ECRAM synapses that exploits activity-dependent conductance modulation with negligible additional circuit overhead. The architecture integrates ECRAM-based synapses with a tunable delay-feedback spike-generation path, enabling transient device dynamics to directly modulate neuron excitability and synaptic efficacy. We used experimentally characterized ECRAM devices exhibiting transient conductance modulation (1.5 KOhms per spike) to develop a compact behavioral model suitable for circuit-level simulation. Circuit simulations demonstrate two key STP behaviors -- synaptic facilitation and intrinsic excitability modulation -- while consuming 2 pJ per spike, and the same device-driven mechanisms extend across multiple neuron topologies. Network-level analysis further demonstrates frequency-selective spike processing, allowing individual synapses to act as tunable temporal filters within spiking neural networks. This work demonstrates that non-equilibrium ECRAM dynamics can serve as a native hardware substrate for STP and temporal computation in neuromorphic circuits.

cs.NE

Realizing Linear Synaptic Plasticity in Electric Double Layer-Gated Transistors for Improved Predictive Accuracy and Efficiency in Neuromorphic Computing

Neuromorphic computing offers a low-power, parallel alternative to traditional von Neumann architectures by addressing the sequential data processing bottlenecks. Electric double layer-gated transistors (EDLTs) resemble biological synapses with their ionic response and offer low power operations, making them suitable for neuromorphic applications. A critical consideration for artificial neural networks (ANNs) is achieving linear and symmetric plasticity (weight updates) during training, as this directly affects accuracy and efficiency. This study uses finite element modeling to explore EDLTs as artificial synapses in ANNs and investigates the underlying mechanisms behind the nonlinear plasticity observed experimentally in previous studies. By solving modified Poisson-Nernst-Planck (mPNP) equations, we examined ion dynamics within an EDL capacitor & their effects on plasticity, revealing that the rates of EDL formation and dissipation are concentration-dependent. Fixed-magnitude pulse inputs result in decreased formation & increased dissipation rates, leading to nonlinear weight updates and limits the number of accessible states and operating range of devices. To address this, we developed a predictive linear ionic weight update solver (LIWUS) in Python to predict voltage pulse inputs that achieve linear plasticity. We then evaluated an ANN with linear and nonlinear weight updates on the MNIST classification task. The LIWUS-provided linear weight updates required 19% fewer epochs in training and validation than the network with nonlinear weight updates to reach optimal performance. It achieved a 97.6% recognition accuracy, 1.5-4.2% higher than with nonlinear updates and a low standard deviation of 0.02%. The network model is amenable to future spiking neural network applications and the performance improvements with linear weight update is expected to increase for complex networks.

physics.app-ph

Analytical Study of KOH Wet Etch Surface Passivation for III-Nitride Micropillars

III-Nitride micropillar structures show great promise for applications in micro light-emitting diodes and vertical power transistors due to their excellent scalability and outstanding electrical properties. Typically, III-Nitride micropillars are fabricated through a top-down approach using reactive ion etch which leads to roughened, non-vertical sidewalls that results in significant performance degradation. Thus, it is essential to remove this plasma etch induced surface damage. Here, we show that potassium hydroxide (KOH) acts as a crystallographic etchant for III-Nitride micropillars, preferentially exposing the vertical <1-100> m-plane, and effectively removing dry etch damage and reducing the structure diameter at up to 36.6 nm/min. Both KOH solution temperature and concentration have a dramatic effect on this wet etch progression. We found that a solution of 20% AZ400K (2% KOH) at 90 C is effective at producing smooth, highly vertical sidewalls with RMS surface roughness as low as 2.59 nm, ideal for high-performance electronic and optoelectronic devices.

physics.app-ph