arXiv subjects

Nobuyuki Yoshikawa

Publications and source records attributed to Nobuyuki Yoshikawa.

16 recordsLinked to original sources

arXiv2026

Ultralow-power coherent qubit control using AQFP logic at millikelvin temperatures

Qubit controllers are essential for scaling superconducting quantum processors, but implementing them at the 10 mK stage of a dilution refrigerator remains challenging due to stringent cooling constraints. Here we report an ultralow-power qubit controller using adiabatic quantum-flux-parametron (AQFP) logic, termed an AQFP-multiplexed qubit controller with virtual Z gates (AQFP QC-VZ). The AQFP QC-VZ generates multi-tone microwave pulses for qubit control with an ultralow power dissipation of 111 pW per qubit. By combining microwave and time-division multiplexing, the AQFP QC-VZ enables parallel application of X and virtual Z gates to multiple qubits using only a few control lines from room temperature. We demonstrate coherent single-qubit gates at the 10 mK stage using an AQFP mixer, a core component of the AQFP QC-VZ, without observable degradation in coherence.

quant-ph↗

arXiv2024

Characterization of Adiabatic Quantum-Flux-Parametrons in the MIT LL SFQ5ee+ Process

Adiabatic quantum-flux-parametron (AQFP) logic is a proven energy-efficient superconductor technology for various applications. To address the scalability challenges, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with more than 2x denser overall designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory. This new process features nine planarized Nb layers with a 0.25 $μ$m minimum linewidth. The fabricated circuits were tested in a liquid He probe and in a closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 $μ$T and about 1.2 $μ$T. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in the denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.

cond-mat.supr-con↗

arXiv2024

SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits

Superconducting circuits, like Adiabatic Quantum-Flux-Parametron (AQFP), offer exceptional energy efficiency but face challenges in physical design due to sophisticated spacing and timing constraints. Current design tools often neglect the importance of constraint adherence throughout the entire design flow. In this paper, we propose SuperFlow, a fully-customized RTL-to-GDS design flow tailored for AQFP devices. SuperFlow leverages a synthesis tool based on CMOS technology to transform any input RTL netlist to an AQFP-based netlist. Subsequently, we devise a novel place-and-route procedure that simultaneously considers wirelength, timing, and routability for AQFP circuits. The process culminates in the generation of the AQFP circuit layout, followed by a Design Rule Check (DRC) to identify and rectify any layout violations. Our experimental results demonstrate that SuperFlow achieves 12.8% wirelength improvement on average and 12.1% better timing quality compared with previous state-of-the-art placers for AQFP circuits.

cs.ET↗

arXiv2024

Microwave-multiplexed qubit controller using adiabatic superconductor logic

Cryogenic qubit controllers (QCs) are the key to build large-scale superconducting quantum processors. However, developing scalable QCs is challenging because the cooling power of a dilution refrigerator is too small (~10 $μ$W at ~10 mK) to operate conventional logic families, such as complementary metal-oxide-semiconductor logic and superconducting single-flux-quantum logic, near qubits. Here we report on a scalable QC using an ultra-low-power superconductor logic family, namely adiabatic quantum-flux-parametron (AQFP) logic. The AQFP-based QC, referred to as the AQFP-multiplexed QC (AQFP-mux QC), produces multi-tone microwave signals for qubit control with an extremely small power dissipation of 81.8 pW per qubit. Furthermore, the AQFP-mux QC adopts microwave multiplexing to reduce the number of coaxial cables for operating the entire system. As a proof of concept, we demonstrate an AQFP-mux QC chip that produces microwave signals at two output ports through microwave multiplexing and demultiplexing. Experimental results show an output power of approximately $-$80 dBm and on/off ratio of ~40 dB at each output port. Basic mixing operation is also demonstrated by observing sideband signals.

physics.app-ph↗

arXiv2023

A Josephson Parametric Oscillator-Based Ising Machine

Ising machines have emerged as a promising solution for rapidly solving NP-complete combinatorial optimization problems, surpassing the capabilities of traditional computing methods. By efficiently determining the ground state of the Hamiltonian during the annealing process, Ising machines can effectively complement CPUs in tackling optimization challenges. To realize these Ising machines, a bi-stable oscillator is essential to emulate the atomic spins and interactions of the Ising model. This study introduces a Josephson parametric oscillator (JPO)-based tile structure, serving as a fundamental unit for scalable superconductor-based Ising machines. Leveraging the bi-stable nature of JPOs, which are superconductor-based oscillators, the proposed machine can operate at frequencies of 7.5GHz while consuming significantly less power (by three orders of magnitude) than CMOS-based systems. Furthermore, the compatibility of the proposed tile structure with the Lechner-Hauke-Zoller (LHZ) architecture ensures its viability for large-scale integration. We conducted simulations of the tile in a noisy environment to validate its functionality. We verified its operational characteristics by comparing the results with the analytical solution of its Hamiltonian model. This verification demonstrates the feasibility and effectiveness of the JPO-based tile in implementing Ising machines, opening new avenues for efficient and scalable combinatorial optimization in quantum computing.

quant-ph↗

arXiv2023

Safe multi-agent motion planning under uncertainty for drones using filtered reinforcement learning

We consider the problem of safe multi-agent motion planning for drones in uncertain, cluttered workspaces. For this problem, we present a tractable motion planner that builds upon the strengths of reinforcement learning and constrained-control-based trajectory planning. First, we use single-agent reinforcement learning to learn motion plans from data that reach the target but may not be collision-free. Next, we use a convex optimization, chance constraints, and set-based methods for constrained control to ensure safety, despite the uncertainty in the workspace, agent motion, and sensing. The proposed approach can handle state and control constraints on the agents, and enforce collision avoidance among themselves and with static obstacles in the workspace with high probability. The proposed approach yields a safe, real-time implementable, multi-agent motion planner that is simpler to train than methods based solely on learning. Numerical simulations and experiments show the efficacy of the approach.

cs.RO↗

arXiv2023

SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices

Adiabatic Quantum-Flux-Parametron (AQFP) is a superconducting logic with extremely high energy efficiency. By employing the distinct polarity of current to denote logic `0' and `1', AQFP devices serve as excellent carriers for binary neural network (BNN) computations. Although recent research has made initial strides toward developing an AQFP-based BNN accelerator, several critical challenges remain, preventing the design from being a comprehensive solution. In this paper, we propose SupeRBNN, an AQFP-based randomized BNN acceleration framework that leverages software-hardware co-optimization to eventually make the AQFP devices a feasible solution for BNN acceleration. Specifically, we investigate the randomized behavior of the AQFP devices and analyze the impact of crossbar size on current attenuation, subsequently formulating the current amplitude into the values suitable for use in BNN computation. To tackle the accumulation problem and improve overall hardware performance, we propose a stochastic computing-based accumulation module and a clocking scheme adjustment-based circuit optimization method. We validate our SupeRBNN framework across various datasets and network architectures, comparing it with implementations based on different technologies, including CMOS, ReRAM, and superconducting RSFQ/ERSFQ. Experimental results demonstrate that our design achieves an energy efficiency of approximately 7.8x10^4 times higher than that of the ReRAM-based BNN framework while maintaining a similar level of model accuracy. Furthermore, when compared with superconductor-based counterparts, our framework demonstrates at least two orders of magnitude higher energy efficiency.

cs.ET↗

arXiv2023

High-Temperature Superconductor Quantum Flux Parametron for Energy-Efficient Logic

As we rapidly advance through the information age, the power consumed by computers, data centers, and networks grows exponentially. This has inspired a race to develop alternative low-power computational technologies. A new adiabatic configuration of a decades-old superconducting digital logic device has darted into the lead called quantum flux parametrons (QFP). QFP operate with dissipation so low that they seemingly violate the laws of thermodynamics. In just a short span of time, they have gone from simple single NOT gates to complex processors containing thousands of gates. They are fabricated from elemental niobium superconductors cooled to just a few degrees above absolute zero. However, their efficiency is so great that for large high-performance computers with several gates, the energy savings are immense. For smaller computational platforms QFPs from high-temperature superconductors (high-Tc) are highly desirable. In this work, we take the first steps towards this goal with the demonstration of a high-T C QFP shift register. Our device is fabricated using focused helium ion beam lithography where the material is modified with an ion beam at the nanoscale to directly pattern these circuits into a high-T C thin film. We validate the correct logical operation at 25 K, over 6 times higher than niobium devices with an estimated bit energy of 0.1 attoJoule at 10 GHz.

physics.app-ph↗

arXiv2023

Low-latency adiabatic quantum-flux-parametron circuit integrated with a hybrid serializer/deserializer

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

physics.app-ph↗

arXiv2021

Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.

cs.ET↗

arXiv2021

An adiabatic superconductor comparator with 46 nA sensitivity

Adiabatic quantum-flux-parametron (AQFP) circuits can operate with extremely small energy dissipation (~1 zJ per junction at 5 GHz) and high sensitivity (~1 μA) owing to adiabatic switching. Thus, AQFP logic is suitable to use as readout interfaces for cryogenic detectors, such as superconducting nanowire single-photon detectors (SSPDs). In order to extend the application of AQFP logic to various detectors, it is crucial to achieve even better sensitivity because some detectors, such as WSi SSPDs and transition edge sensors (TESs), require sub-μA sensitivity. In the present study, we propose a high-sensitivity AQFP comparator with a current transformer (CT), which increases the equivalent input current and thereby improves the sensitivity. Numerical simulation shows that the proposed comparator achieves a sensitivity approximately six times better than that of a conventional AQFP comparator. Furthermore, we demonstrate a sensitivity of 46 nA at 4.2 K for a sampling frequency of 500 Hz in the experiment.

physics.app-ph↗

arXiv2021

Impedance Design of Excitation Lines in Adiabatic Quantum-Flux-Parametron Logic Using InductEx

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic family that utilizes adiabatic switching. AQFP gates are powered and clocked by ac excitation current; thus, to operate AQFP circuits at high clock frequencies, it is required to carefully design the characteristic impedance of excitation lines (especially, above AQFP gates) so that microwave excitation current can propagate without reflections in the entire circuit. In the present study, we design the characteristic impedance of the excitation line using InductEx, which is a three-dimensional parameter extractor for superconductor devices. We adjust the width of an excitation line using InductEx such that the characteristic impedance becomes 50 Ω even above an AQFP gate. Then, we fabricate test circuits to verify the impedance of the excitation line. We measure the impedance using the time domain reflectometry (TDR). We also measure the S parameters of the excitation line to investigate the maximum available clock frequency. Our experimental results indicate that the characteristic impedance of the excitation line agrees well with the design value even above AQFP gates, and that clock frequencies beyond 5 GHz are available in large-scale AQFP circuits.

physics.app-ph↗

arXiv2020

Stability-Certified Reinforcement Learning via Spectral Normalization

In this article, two types of methods from different perspectives based on spectral normalization are described for ensuring the stability of the system controlled by a neural network. The first one is that the L2 gain of the feedback system is bounded less than 1 to satisfy the stability condition derived from the small-gain theorem. While explicitly including the stability condition, the first method may provide an insufficient performance on the neural network controller due to its strict stability condition. To overcome this difficulty, the second one is proposed, which improves the performance while ensuring the local stability with a larger region of attraction. In the second method, the stability is ensured by solving linear matrix inequalities after training the neural network controller. The spectral normalization proposed in this article improves the feasibility of the a-posteriori stability test by constructing tighter local sectors. The numerical experiments show that the second method provides enough performance compared with the first one while ensuring enough stability compared with the existing reinforcement learning algorithms.

cs.AI↗

arXiv2020

Scalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families

We propose a scalable readout interface for superconducting nanowire single-photon detector (SSPD) arrays, which we call the AQFP/RSFQ interface. This interface is composed of adiabatic quantum-flux-parametron (AQFP) and rapid single-flux-quantum (RSFQ) logic families. The AQFP part reads out the spatial information of an SSPD array via a single cable, and the RSFQ part reads out the temporal information via a single cable. The hybrid interface has high temporal resolution owing to low timing jitter in the operation of the RSFQ part. In addition, the hybrid interface achieves high circuit scalability because of low supply current in the operation of the AQFP part. Therefore, the hybrid interface is suitable for handling many-pixel SSPD arrays. We demonstrate a four-pixel SSPD array using the hybrid interface as proof of concept. The measurement results show that the hybrid interface can read out all of the pixels with a low error rate and low timing jitter.

physics.ins-det↗

arXiv2019

Systematic method to evaluate energy dissipation in adiabatic quantum-flux-parametron logic

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic. It operates with zero static power dissipation and very low dynamic power dissipation owing to adiabatic switching. In previous numerical studies, we have evaluated the energy dissipation of basic AQFP logic gates and demonstrated sub-kBT switching energy, where kB is the Boltzmann's constant and T is the temperature, by integrating the product of the excitation current and voltage associated with the gates over time. However, this method is not applicable to complex logic gates, especially those in which the number of inputs is different from the number of outputs. In the present study, we establish a systematic method to evaluate the energy dissipation of general AQFP logic gates. In the proposed method, the energy dissipation is calculated by subtracting the energy dissipation of the peripheral circuits from that of the entire circuit. In this way, the energy change due to the interaction between gates, which makes it difficult to evaluate the energy dissipation, can be deducted. We evaluate the energy dissipation of a majority gate using this method.

cs.ET↗

arXiv2019

A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology

The Adiabatic Quantum-Flux-Parametron (AQFP) superconducting technology has been recently developed, which achieves the highest energy efficiency among superconducting logic families, potentially huge gain compared with state-of-the-art CMOS. In 2016, the successful fabrication and testing of AQFP-based circuits with the scale of 83,000 JJs have demonstrated the scalability and potential of implementing large-scale systems using AQFP. As a result, it will be promising for AQFP in high-performance computing and deep space applications, with Deep Neural Network (DNN) inference acceleration as an important example. Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature since each AQFP logic gate is connected with an AC clock signal, which increases the difficulty to avoid RAW hazards; the second is the unique opportunity of true random number generation (RNG) using a single AQFP buffer, far more efficient than RNG in CMOS. We point out that these two characteristics make AQFP especially compatible with the \emph{stochastic computing} (SC) technique, which uses a time-independent bit sequence for value representation, and is compatible with the deep pipelining nature. Further, the application of SC has been investigated in DNNs in prior work, and the suitability has been illustrated as SC is more compatible with approximate computations. This work is the first to develop an SC-based DNN acceleration framework using AQFP technology.

cs.NE↗