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Noriyuki Miura

Publications and source records attributed to Noriyuki Miura.

2 recordsLinked to original sources

PrometheusFree: Concurrent Detection of Laser Fault Injection Attacks in Optical Neural Networks

Silicon Photonics-based AI Accelerators (SPAAs) have been considered as promising AI accelerators achieving high energy efficiency and low latency. While many researchers focus on improving SPAAs' energy efficiency and latency, their physical security has only recently received attention. While it is essential to deliver strong optical neural network inferencing approaches, their success and adoption are predicated on their ability to deliver a secure execution environment. Towards this end, this paper proposes PrometheusFree, an optical neural network framework that is capable of concurrent detection of laser fault injection attacks. This paper first presents an illustrative threat of laser fault injection attacks on SPAAs, capable of subjecting the optical neural network to misclassifications. The threat then is addressed in this paper by developing techniques for concurrent detection of the laser fault injection attacks. Furthermore, this paper introduces a novel application of Wavelength Division Perturbation (WDP) technique where wavelength-dependent Vector Matrix Multiplication (VMM) results are utilized to boost fault attack detection accuracy. Simulation results show that PrometheusFree achieves over 96% attack-caused misprediction recall as the use of the WDP technique squashes the attack success rate by 38.6% on average. Compared with prior art, PrometheusFree limits the average attack success ratio to 0.019, yielding a 95.3% reduction. The experimental results confirm the superiority of the concurrent detection and the boost in attack detection abilities imparted by the WDP approaches.

physics.optics↗

Lapis SOI Pixel Process

0.2 um fully-depleted SOI technology has been developed a for X-ray pixel detectors. To improve the detector performance, some advanced process technologies are developing continuously. To utilize the high resistivity FZ-SOI, slow ramp up and ramp down recipes are applied for the thermal processes in both of SOI wafer fabrication and pixel detector process. The suitable backside treatment is also applied to prevent increase of leakage current at backside damaged layer in the case of full depletion of substrate. Large detector chip about 66mm width and 30mm height can be obtained by stitching exposure technique for large detector chip. To improve cross-talk and radiation tolerance, the nested well structure and double- SOI wafer are now under investigation for advanced pixel structure.

physics.ins-det↗