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Noriyuki Sato

Publications and source records attributed to Noriyuki Sato.

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Solid-state transcapacitor, a new gain element for logic, memory and interconnects

Today's transistors dictate the voltage and charge scales for both logic and memory. While AI systems are recognized to be limited by memory energy, the dominant share of the energy is expended in the intrachip interconnects whose voltage and charge scales are set by transistors. The energy scaling challenges of transistors can be attributed to simultaneously meeting high current density, high current/impedance modulation, and the inability to lower voltages. Hence, a new logic element that lowers the voltage and charge needs is a priority, not only for lowering logic power but also memory access power. Here, we propose a novel 3-terminal logic element for low energy computing, a solid-state transcapacitor (TCAP). A TCAP is a solid state displacement current modulator realized by a gate which controls the charge-voltage relationship of the channel. Unlike transistors, TCAPs eliminate the dissipative transport current, are not bound by the Boltzmann current modulation limit, and operate with displacement currents limited only by the polarization response and contact resistance. Hence, TCAP circuits may simultaneously overcome the voltage, current density, and current modulation limits of CMOS. We describe a solid state TCAP using a piezoelectric transcapacitor in which a gate-controlled stressor modulates the capacitance of a polar channel via electromechanical coupling. This device achieves inversion and gain, essential for logic, and is functionally equivalent to a 1T-1C memory cell, enabling dense memory. Using voltage scaling, capacitive energy recovery, and high polarization densities of polar materials, the logic based on TCAP offers a pathway to 100 fold lower energy consumption with a delay comparable to ultimately scaled CMOS devices. This approach provides a new potential pathway for low-energy computing beyond the limits of transistors using electro-mechanics and multiferroics.

cond-mat.mes-hall

Two-terminal spin-orbit torque magnetoresistive random access memory

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is an attractive alternative to current random access memory technologies due to its non-volatility, fast operation and high endurance. STT-MRAM does though have limitations including the stochastic nature of the STT-switching and a high critical switching current, which makes it unsuitable for ultrafast operation at nanosecond and sub-nanosecond regimes. Spin-orbit torque (SOT) switching, which relies on the torque generated by an in-plane current, has the potential to overcome these limitations. However, SOT-MRAM cells studied so far use a three-terminal structure in order to apply the in-plane current, which increases the size of the cells. Here we report a two-terminal SOT-MRAM cell based on a CoFeB/MgO magnetic tunnel junction pillar on an ultrathin and narrow Ta underlayer. In this device, an in-plane and out-of-plane current are simultaneously generated upon application of a voltage, and we demonstrate that the switching mechanism is dominated by SOT. We also compare our device to a STT-MRAM cell built with the same architecture and show that critical write current in the SOT-MRAM cell is reduced by more than 70%.

cond-mat.mes-hall