arXiv subjects

Oded Wertheim

Publications and source records attributed to Oded Wertheim.

5 recordsLinked to original sources

arXiv2025

Impacts of Decoder Latency on a Utility-Scale Quantum Computer Architecture

The speed of a fault-tolerant quantum computer depends in large part on the reaction time of its classical electronics, that is, the total time required by decoders and controllers to determine the outcome of a logical measurement and execute subsequent conditional logical operations. Despite its importance, the reaction time and its impact on the design of a logical microarchitecture of a quantum computer are not well understood. In this work, we perform a detailed system-level analysis of the classical and quantum resource requirements of a surface code based architecture. To this end, we construct a model of the reaction time in which the decoder latency is based on parallel space- and time-window decoding methods. In addition, we draw communication latencies from our envisioned quantum execution environment, which comprises a high-speed network of quantum processing units, controllers, decoders, and high-performance computing nodes. We use this model to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. We then show how the microarchitecture can be optimized with respect to the reaction time, and present full-system quantum resource estimates based on realistic hardware noise parameters for executing utility-scale quantum circuits of the Fermi-Hubbard model (2562 logical qubits and $4$$\times$$10^6$ $T$ gates) and NMR spectral prediction (241 logical qubits and $5.11$$\times$$10^{11}$ $T$ gates). We numerically determine the impact of improving reaction time on the code distance required for the core processor and on the size of the resource state factory. Moreover, we analyze how decoder speeds constrain the size of practically executable circuits, and show that state-of-the-art decoders will require a performance improvement of at least an order of magnitude to execute utility-scale quantum algorithms within days.

quant-ph↗

arXiv2024

Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.

quant-ph↗

arXiv2024

How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits

In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits. Nevertheless, there are significant outstanding challenges in quantum hardware, fabrication, software architecture, and algorithms on the path towards a full-stack scalable quantum computing technology. Here, we provide a comprehensive review of these scaling challenges. We show how to facilitate scaling by adopting existing semiconductor technology to build much higher-quality qubits, employing systems engineering approaches, and performing distributed heterogeneous quantum-classical computing. We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation. We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration. Furthermore, we introduce high-performance architectures for quantum-probabilistic computing with custom-designed accelerators to tackle today's industry-scale classical optimization, machine learning, and quantum simulation tasks in a cost-effective manner.

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arXiv2023

Quantum-classical processing and benchmarking at the pulse-level

Towards the practical use of quantum computers in the NISQ era, as well as the realization of fault-tolerant quantum computers that utilize quantum error correction codes, pressing needs have emerged for the control hardware and software platforms. In particular, a clear demand has arisen for platforms that allow classical processing to be integrated with quantum processing. While recent works discuss the requirements for such quantum-classical processing integration that is formulated at the gate-level, pulse-level discussions are lacking and are critically important. Moreover, defining concrete performance benchmarks for the control system at the pulse-level is key to the necessary quantum-classical integration. In this work, we categorize the requirements for quantum-classical processing at the pulse-level, demonstrate these requirements with a variety of use cases, including recently published works, and propose well-defined performance benchmarks for quantum control systems. We utilize a comprehensive pulse-level language that allows embedding universal classical processing in the quantum program and hence allows for a general formulation of benchmarks. We expect the metrics defined in this work to form a solid basis to continue to push the boundaries of quantum computing via control systems, bridging the gap between low-level and application-level implementations with relevant metrics.

quant-ph↗

arXiv2023

Benchmarking the ability of a controller to execute quantum error corrected non-Clifford circuits

Reaching fault-tolerant quantum computation relies on the successful implementation of non-Clifford circuits with quantum error correction (QEC). In QEC, quantum gates and measurements encode quantum information into an error-protected Hilbert space, while classical processing decodes the measurements into logical errors. QEC non-Clifford gates pose the greatest computation challenge from the classical controller perspective, as they require mid-circuit decoding-dependent feed-forward, modifying the physical gate sequence based on the decoding outcome of previous measurements within the same circuit. In this work, we introduce the first benchmarks to holistically evaluate the capability of a combined controller-decoder system to run non-Clifford QEC circuits. We show that executing an error-corrected non-Clifford circuit, comprised of numerous non-Clifford gates, strictly hinges upon the classical controller-decoder system. Particularly, its ability to perform decoding-based feed-forward with low-latency, defined as the time between the last measurement required for decoding and the dependent mid-circuit quantum operation. We analyze how the system latency dictates the circuit operational regime: latency divergence, classical-controller-limited runtime, or quantum-operation-limited runtime. Based on this understanding, we introduce latency-based benchmarks to set a standard for developing QEC control systems as an essential components of fault-tolerant quantum computation.

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