RFNoC-Based FPGA Offloading for Fully Programmable PHY Acceleration
Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip (RFNoC) based hardware acceleration framework that offloads key physical layer procedures to a field programmable gate array (FPGA). The proposed design accelerates procedures, including low density parity check codes (LDPC) encoding and decoding, rate matching and unmatching, interleaving and deinterleaving, scrambling and descrambling, and log likelihood ratio estimation. The accelerator is integrated directly into the OpenAirInterface radio access network software, enabling simultaneous use of the FPGA as driver of the radio front end and a high throughput accelerator. The proposed system is validated through real time experiments with a commercial smartphone successfully connecting to the network. The implementation results demonstrate that a throughput of about 900 Mbps is achiievable using a moderate FPGA resource utlization.