P. Mastrandrea | Searcharxiv

arXiv2023

Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC

The fast reconstruction of charged particle tracks with high efficiency and track quality is an essential part of the online data selection for the ATLAS experiment at the High-Luminosity LHC. Dedicated custom designed hardware boards and software simulations have been developed to assess the feasibility of a Hardware Tracking Trigger (HTT) system. The Pattern Recognition Mezzanine (PRM), as part of the HTT system, has been designed to recognize track candidates in silicon detectors with Associative Memory ASICs and to select and reconstruct tracks using linearized algorithms implemented in an Intel Stratix 10 MX FPGA. The highly parallelized FPGA design makes extensive use of the integrated High-Bandwidth-Memory. In this paper, the FPGA design for the PRM board is presented. Its functionalities have been verified in both simulations and hardware tests on an Intel Stratix 10 MX development kit.

physics.ins-det↗

arXiv2020

Cooling and Timing tests of the ATLAS Fast Tracker VME boards

The Fast Tracker (FTK) is an ATLAS trigger upgrade built for full event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The Associative Memory Board Serial Link Processor (AMB) and the Auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the Processing Unit (PU), which finds tracks using hits from 8 layers of the inner detector. The PU works in pipeline with the Second Stage Board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and 4 SSBs are installed in a VME crate. The high power-consumption of the AMB, AUX and SSB (respectively of about 250 W, 70 W and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared to a common VME setup, the 8 FTK core crates will use $\approx$ 60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and 8 SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.

physics.ins-det↗