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Patrick Harvey-Collard

Publications and source records attributed to Patrick Harvey-Collard.

20 records · Page 2Linked to original sources

A Silicon Nanocrystal Tunnel Field Effect Transistor

In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very thin silicon dioxyde and the channel in intrinsic polycrystalline silicon. The absence of doping eliminates the problem of achieving sharp doping profiles at the junctions, which has proven a challenge for large-scale integration and in principle allows scaling down the atomic level. The demonstrated ncFET features a 10$^4$ on/off current ratio at room temperature, a low 30 pA/$μ$m leakage current at a 0.5 V bias, an on-state current on a par with typical all-Si TFETs and bipolar operation with high symmetry. Quantum dot transport spectroscopy is used to assess the band structure and energy levels of the silicon island.

cond-mat.mes-hall↗

Inductively Coupled Plasma etching of amorphous silicon nanostructures over nanotopography using C4F8/SF6 chemistry

Inductively Coupled Plasma (ICP) etching of amorphous silicon (a-Si) nanostructures using a continuous C4F8/SF6 plasma over nanotopography in silicon dioxide (SiO2) is investigated. The coil power of the ICP system is used to tune the a-Si etch rate from 20 to 125 nm/min. The etch rates of a-Si, SiO2 and electroresist are measured depending on the SF6 ratio, platen power and chamber pressure and used to optimize the a-Si:SiO2 etch selectivity. The results on nanostructures show that the presence of an insulating etch-stop layer affects the passivation ratio required to achieve vertical sidewalls. A low pressure is also necessary in order to etch the silicon nanostructure embedded into the oxide nanotrenches to form a highly conformable a-Si nanowire. We argue that both of these behaviors could be explained by surface charging effects. Finally, etching of 20 nm a-Si nanowires that cross 15 nm trenches in oxide with vertical sidewalls and a 4.3:1 a-Si:SiO2 etch selectivity is demonstrated. This etching process can be used in applications where nanotopography is present such as single electron transistors or multigate transistors.

physics.plasm-ph↗