arXiv subjects

Paul C. McIntyre

Publications and source records attributed to Paul C. McIntyre.

8 recordsLinked to original sources

arXiv2026

Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $μ$A $μ$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$κ$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

cond-mat.mtrl-sci↗

arXiv2026

Shining light on short-range atomic ordering in semiconductors alloys

The functional properties of semiconductors are typically controlled by tailoring their chemical composition and their state of strain, and by controlling their long-range structural order, including the presence of extended defects such as dislocations. In addition to these approaches, theoretical predictions suggest that short-range order (SRO) of atoms in group-IV semiconductor alloys can modify the bandgap, a defining property of any semiconductor. Herein, a new machine learning enabled, computation-guided methodology for extended X-ray absorption fine structure (EXAFS) analysis of SRO is used to quantify the effects of local atomic order on the bandgap of germanium-tin (GeSn) alloy single crystal nanostructures with well-controlled strain and composition. Correlative analysis of EXAFS and photoluminescence (PL) establishes the relationship between bandgap and the Warren-Cowley short-range order (WC-SRO) parameter of the GeSn alloys. It is further demonstrated that SRO can be tuned over a broad range by post-deposition annealing of the alloy crystals. This work establishes control of SRO as an important design parameter for semiconducting properties and suggests the potential for quantitative measurement and tuning of SRO in other semiconductor alloy systems.

cond-mat.mtrl-sci↗

arXiv2025

Channel-last gate-all-around nanosheet oxide semiconductor transistors

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

cond-mat.mtrl-sci↗

arXiv2025

Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

cond-mat.mtrl-sci↗

arXiv2022

Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies

Semiconductor innovation drives improvements to technologies that are critical to modern society. The country that successfully accelerates semiconductor innovation is positioned to lead future semiconductor-driven industries and benefit from the resulting economic growth. It is our view that a next generation infrastructure is necessary to accelerate and enhance semiconductor innovation in the U.S. In this paper, we propose such an advanced infrastructure composed of a national network of facilities with enhancements in technology and business models. These enhancements enable application-driven and challenge-based research and development, and ensure that facilities are accessible and sustainable. The main tenets are: a challenge-driven operational model, a next-generation infrastructure to serve that operational model, technology innovations needed for advanced facilities to speed up learning cycles, and innovative cost-effective business models for sustainability. Ultimately, the expected outcomes of such a participatory, scalable, and sustainable nation-level advanced infrastructure will have tremendous impact on government, industry, and academia alike.

cs.OH↗

arXiv2021

Low Resistance III-V Hetero-contacts to N-Ge

We experimentally study III-V/Ge heterostructure and demonstrate InGaAs hetero-contacts to n-Ge with a wide range of In % and achieve low contact resistivity ($ρ_C$) of $5\times10^{-8} Ω\cdot cm^2$ for Ge doping of $3 \times 10^{19} cm^{-3}$. This results from re-directing the charge neutrality level (CNL) near the conduction band and benefiting from low effective mass for high electron transmission. For the first time, we observe that the heterointerface presents no temperature dependence despite the two different conduction minimum valley locations of III-V ($Γ$-valley) and Ge (L-valley), which potentially stems from elastic trap-assisted tunneling through defect states at the interface generated by dislocations. The hetero-interface plays a dominant role in the overall $ρ_C$ below $\approx 1 \times 10^{-7} Ω\cdot cm^2$, which can be further improved with large active dopant concentration in Ge by co-doping.

cond-mat.mtrl-sci↗

arXiv2014

Control of InGaAs facets using metal modulation epitaxy (MME)

Control of faceting during epitaxy is critical for nanoscale devices. This work identifies the origins of gaps and different facets during regrowth of InGaAs adjacent to patterned features. Molecular beam epitaxy (MBE) near SiO2 or SiNx led to gaps, roughness, or polycrystalline growth, but metal modulated epitaxy (MME) produced smooth and gap-free "rising tide" (001) growth filling up to the mask. The resulting self-aligned FETs were dominated by FET channel resistance rather than source-drain access resistance. Higher As fluxes led first to conformal growth, then pronounced {111} facets sloping up away from the mask.

cond-mat.mtrl-sci↗

arXiv2010

Nucleation and growth of germanium islands during layer exchange metal-induced crystallization

Al-induced layer exchange crystallization of amorphous Ge thin films has been demonstrated recently, and provides a suitable system to characterize, model and control Ge crystal growth on non-crystalline substrates. Direct observation of Ge transfer to the surface of Al through an interposed GeOx interfacial layer allows independent measurement of the density and average area of crystalline Ge islands formed on the surface. Based on these experimental observations, the Johnson-Mehl-Avrami-Kologoromov phase transformation theory is extended to model nanoscale nucleation and growth of Ge islands in two dimensions. The Ge island growth mechanism switches from atomic-attachment-limited to surface diffusion-limited kinetics with increasing time. The transition point between these regimes depends on the Ge nucleation site density and the annealing temperature. Finally, we show that local bias-voltage stressing of the interfacial layer controls the areal density of nucleated Ge islands on the film surface.

cond-mat.mtrl-sci↗