arXiv subjects

Paul Coote

Publications and source records attributed to Paul Coote.

4 recordsLinked to original sources

arXiv2026

Experimental demonstration of the Quantum Fourier Transform on up to 100 qubits using a convolutional compilation strategy

We present and experimentally validate the `Convolutional QFT': a constructive compilation strategy for the Quantum Fourier Transform (QFT) subroutine on a linear nearest neighbor (LNN) qubit topology. We first introduce a novel strategy that compiles the $n$-qubit QFT onto an LNN topology using only $n^2 - n$ $CX$ gates, matching requirements of a direct compilation on an all-to-all architecture. We then derive the convolutional variant used in our experiments, which requires an additional two $CX$ gates in total, and is realized via a compact, translation-invariant kernel circuit gadget that traverses a quantum register. We demonstrate the power of the convolutional compilation strategy on the IBM Quantum Platform by executing QFT benchmarking circuits. We measure a process fidelity of 11.4% at 50 qubits, and 1.8% at 80 qubits. The correct output state remains clearly distinguishable above background noise up to 100 qubits. These results constitute the largest experimental QFT demonstrated on any quantum computing hardware to date.

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arXiv2026

Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting

Quantum computer hardware is predicted to scale over hundreds of thousands of qubits coming online in the next decade. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of $1,000$ logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551x reduction in algorithmic logical error and up to 138x reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 days, which can be reduced to 4.9 days via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 days. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.

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arXiv2025

No need to calibrate: characterization and compilation for high-fidelity circuit execution using imperfect gates

We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default $CX$ gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.

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arXiv2024

Resource-efficient context-aware dynamical decoupling embedding for arbitrary large-scale quantum algorithms

We introduce and implement GraphDD: an efficient method for real-time, circuit-specific, optimal embedding of dynamical decoupling (DD) into executable quantum algorithms. We demonstrate that for an arbitrary quantum circuit, GraphDD exactly refocuses both quasi-static single-qubit dephasing and crosstalk idling errors over the entire circuit, while using a minimal number of additional single-qubit gates embedded into idle periods. The method relies on a graph representation of the embedding problem, where the optimal decoupling sequence can be efficiently calculated using an algebraic computation that scales linearly with the number of idles. This allows optimal DD to be embedded during circuit compilation, without any calibration overhead, additional circuit execution, or numerical optimization. The method is generic and applicable to any arbitrary circuit; in compiler runtime the specific pulse-sequence solutions are tailored to the individual circuit, and consider a range of contextual information on circuit structure and device connectivity. We verify the ability of GraphDD to deliver enhanced circuit-level error suppression on 127-qubit IBM devices, showing that the optimal circuit-specific DD embedding resulting from GraphDD provides orders of magnitude improvements to measured circuit fidelities compared with standard embedding approaches available in Qiskit.

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