arXiv subjects

Paul Schnabl

Publications and source records attributed to Paul Schnabl.

4 recordsLinked to original sources

arXiv2026

Parity-unfolded distillation architecture for noise-biased platforms

We introduce the parity-unfolded architecture, a fault-tolerant quantum computing scheme that relies on direct preparation and teleportation of small-angle rotations $ Z^{1/2^{k}}$ rather than approximating them with the conventional (Clifford + $T$) gate set. The architecture is enabled by efficient distillation of gates from an arbitrary level of the Clifford hierarchy, which we refer to as parity unfolding. With it, a state $|Z_k\rangle = Z^{1/2^{k}}|{+}\rangle$ can be prepared fault-tolerantly using $2^{k+3} + O(2^{k/2})$ biased-noise qubits on a planar chip with nearest-neighbour connectivity. For algorithms requiring native $Z^{1/2^{k}}$ gates, such as the Quantum Fourier Transform and phase estimation, the proposed scheme allows to reduce resource overheads for up to $k=7$, i.e., up to $T^{1/32}$. Furthermore, when used for the synthesis of arbitrary small-angle rotations, parity-unfolded distillation of ($T$ + $\sqrt{T}$) reduces the minimum achievable logical error rate by 43% while cutting the resource requirements by 26%, when compared to unfolded distillation of only the $T$ gate.

quant-ph↗

arXiv2025

Leveraging biased noise for more efficient quantum error correction at the circuit-level with two-level qubits

Tailoring quantum error correction codes (QECC) to biased noise has demonstrated significant benefits. However, most of the prior research on this topic has focused on code capacity noise models. Furthermore, a no-go theorem prevents the construction of CNOT gates for two-level qubits in a bias preserving manner which may, in principle, imply that noise bias cannot be leveraged in such systems. In this work, we show that a residual bias up to $\eta\sim$5 can be maintained in CNOT gates under certain conditions. Moreover, we employ controlled-phase (CZ) gates in syndrome extraction circuits and show how to natively implement these in a bias-preserving manner for a broad class of qubit platforms. This motivates the introduction of what we call a hybrid biased-depolarizing (HBD) circuit-level noise model which captures these features. We numerically study the performance of the XZZX surface code and observe that bias-preserving CZ gates are critical for leveraging biased noise. Accounting for the residual bias present in the CNOT gates, we observe an increase in the code threshold up to a $1.27\%$ physical error rate, representing a $90\%$ improvement. Additionally, we find that the required qubit footprint can be reduced by up to a $75\%$ at relevant physical error rates.

quant-ph↗

arXiv2025

Optimal Decoder for the Error Correcting Parity Code

We present a two-step decoder for the parity code and evaluate its performance in code-capacity and faulty-measurement settings. For noiseless measurements, we find that the decoding problem can be reduced to a series of repetition codes while yielding near-optimal decoding for intermediate code sizes and achieving optimality in the limit of large codes. In the regime of unreliable measurements, the decoder demonstrates fault-tolerant thresholds above 5% at the cost of decoding a series of independent repetition codes in (1 + 1) dimensions. Such high thresholds, in conjunction with a practical decoder, efficient long-range logical gates, and suitability for planar implementation, position the parity architecture as a promising candidate for demonstrating quantum advantage on qubit platforms with strong noise bias.

quant-ph↗

arXiv2025

SpinHex: A low-crosstalk, spin-qubit architecture based on multi-electron couplers

Semiconductor spin qubits are an attractive quantum computing platform that offers long qubit coherence times and compatibility with existing semiconductor fabrication technology for scale up. Here, we propose a spin-qubit architecture based on spinless multielectron quantum dots that act as low-crosstalk couplers between a two-dimensional arrangement of spin-qubits in a hexagonal lattice. The multielectron couplers are controlled by voltage signals, which mediate fast Heisenberg exchange and thus enable coherent multi-qubit operations. For the proposed architecture, we discuss the implementation of the rotated XZZX surface code and numerically study its performance for a circuit-level noise model. We predict a threshold of $0.18\%$ for the error rate of the entangling gates. We further evaluate the scalability of the proposed architecture and predict the need for $4480$ physical qubits per logical qubit with logical error rates of $10^{-12}$ considering entangling gate fidelities of $99.99\%$, resulting in a chip size of $2.6$cm$^2$ to host $10,000$ logical qubits.

quant-ph↗