arXiv subjects

Paul Steinacker

Publications and source records attributed to Paul Steinacker.

11 recordsLinked to original sources

arXiv2026

Machine Learning for Charge State Characterization of Isolated Double Quantum Dots

Scaling semiconductor quantum dot arrays toward fault-tolerant quantum computing requires efficient tuneup of spin qubits, a process that depends on the analysis of charge stability maps (CSMs) and remains largely manual. While machine learning has been widely applied to CSM analysis in reservoir-coupled devices, automated tuning in the increasingly important isolated-mode regime has received limited attention. In isolated-mode CSMs, charge transitions appear as near-vertical lines, making them well suited to compact, task-specific models. We present two convolutional neural networks with fewer than one million parameters, trained on CSMs collected from 32 silicon metal-oxide-semiconductor (SiMOS) double-quantum-dot devices measured at approximately 1 K using an automated cryogenic probing system. Sixteen devices were used for training and sixteen were held out to evaluate cross-device generalization against hand-labeled ground truth. CSMClassifier identifies charge instability and sensor artifacts, achieving 94% macro-averaged accuracy across three quality classes on 2,407 held-out images. ChargeLineNet localizes charge-transition lines and determines electron occupancy, achieving 95.3% exact line-count accuracy on 1,131 held-out images. Combined into a single pipeline, the models correctly determine electron occupancy for 93.8% of clean held-out images. Pre-training on synthetic images substantially improves label efficiency. Fine-tuning the pre-trained model on limited experimental data maintains over 90% accuracy, whereas training from scratch degrades significantly under the same conditions. Together, the two models occupy only 6.5 MB and process images in less than 60 ms on standard laboratory hardware, demonstrating a practical path toward scalable, automated characterization and tuneup of quantum-dot devices.

cond-mat.mes-hall↗

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2026

Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

quant-ph↗

arXiv2026

Multi-Qubit Entanglement of Unit Cell Pairs in SiMOS

Spin qubits in silicon-MOS (SiMOS) quantum dots have recently demonstrated compatibility with existing industry standard CMOS fabrication techniques. These devices have routinely achieved single- and two-qubit gate fidelities above 99% and demonstrated highly entangled two-qubit Bell states in isolated double quantum dot (DQD) unit cells, however coupling between unit cells has remained challenging. In this work, we present a two unit cell, four-qubit SiMOS processor with universal controllability and fully parallelised state initialisation and readout. We use this processor to generate maximally entangled three-qubit states, including the Greenberger-Horne-Zeilinger (GHZ) state, and certify multipartite entanglement through violation of the classical Mermin-witness bound. By using a fully symmetric dynamically decoupled gate sequence to create our entangled states, we are able to preserve the lifetime of the entanglement beyond $T_2^*$, to a time limited instead by $T_2^\textrm{Hahn}$. These demonstrations pave a road to the scalable operation of larger SiMOS processors, and achieving high purity, long-lived multi-qubit entangled states in them.

quant-ph↗

arXiv2025

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2)$~\mu$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4)$~$ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

quant-ph↗

arXiv2025

Maximizing the nondemolition nature of a quantum measurement via an adaptive readout protocol

Quantum error correction (QEC) requires non-invasive measurements for fault tolerant quantum computing. Deviations from ideal quantum non-demolition (QND) measurements can disturb the encoded information. To address this challenge, we develop a readout protocol for a $D-$dimensional system that, after a single positive outcome, switches to probing only the $D{-}1$ remaining subspace. This adaptive switching strategy minimizes measurement-induced errors by relying on negative-result measurement results that do not perturb the Hamiltonian. We apply the protocol on an 8-dimensional $^{123}{\rm Sb}$ nuclear qudit in silicon, and achieve an increase in the readout fidelity from $(98.93\pm0.07)\%$ to $(99.61\pm0.04)\%$, while reducing threefold the overall readout time. To highlight the broader relevance of measurement-induced errors, we study a 10-dimensional $^{73}{\rm Ge}$ nuclear spin read out through Pauli spin blockade, revealing nuclear spin flips arising from hyperfine and quadrupole interactions. These results unveil the effect of non-ideal QND readout across diverse platforms, and introduce an efficient readout protocol that can be implemented with minimal FPGA logic on existing hardware.

quant-ph↗

arXiv2025

Coupling a $^{73}$Ge nuclear spin to an electrostatically defined quantum dot

Single nuclear spins in silicon are a promising resource for quantum technologies due to their long coherence times and excellent control fidelities. Qubits and qudits have been encoded on donor nuclei, with successful demonstrations of Bell states and quantum memories on the spin-1/2 $^{31}$P and cat-qubits on the spin-7/2 $^{123}$Sb nuclei. Isoelectronic nuclear spins coupled to gate-defined quantum dots, such as the naturally occurring $^{29}$Si isotope, possess no additional charge and allow for the coupled electron to be shuttled without destroying the nuclear spin coherence. Here, we demonstrate the coupling and readout of a spin-9/2 $^{73}$Ge nuclear spin to a gate-defined quantum dot in SiMOS. The $^{73}$Ge nucleus was implanted by isotope-selective ion-implantation. We observe the hyperfine interaction (HFI) to the coupled quantum dot electron and are able to tune it from 180 kHz to 350 kHz, through the voltages applied to the lateral gate electrodes. This work lays the foundation for future spin control experiments on the spin-9/2 qudit as well as more advanced experiments such as entanglement distribution between distant nuclear spins or repeated weak measurements.

cond-mat.mes-hall↗

arXiv2025

Interplay of Zeeman Splitting and Tunnel Coupling in Coherent Spin Qubit Shuttling

Spin shuttling offers a promising approach for developing scalable silicon-based quantum processors by addressing the connectivity limitations of quantum dots. In this work, we demonstrate high-fidelity bucket-brigade spin shuttling in a silicon MOS device, utilizing Pauli-spin-blockade readout. We achieve an average shuttling fidelity of \SI{99.8}{\percent}. The residual shuttling error is highly sensitive to the ratio between interdot tunnel coupling and Zeeman splitting, with tuning of these parameters enabling up to a 20-fold variation in error rate. An appropriate four-level Hamiltonian model supports our findings. These results provide valuable insights for optimizing high-performance spin-shuttling systems in future quantum architectures.

cond-mat.mes-hall↗

arXiv2024

A 300 mm foundry silicon spin qubit unit cell exceeding 99% fidelity in all operations

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99% and state preparation and measurement fidelity exceeds 99.9%, as evidenced by gate set tomography (GST). We report coherence and lifetimes up to $T_\mathrm{2}^{\mathrm{*}} = 30.4$ $\mu$s, $T_\mathrm{2}^{\mathrm{Hahn}} = 803$ $\mu$s, and $T_1 = 6.3$ s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes, solvable with further isotopic purification, rather than charge noise arising from the dielectric environment. Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology.

cond-mat.mes-hall↗

arXiv2024

Violating Bell's inequality in gate-defined quantum dots

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99 %, including state preparation and measurement (SPAM). We demonstrate a 97.17 % Bell state fidelity without correcting for readout errors and violate Bell's inequality with a Bell signal of S = 2.731 close to the theoretical maximum of $2\sqrt{2}$. Our measurements exceed the classical limit even at elevated temperatures of 1.1 K or entanglement lifetimes of 100 $\mu s$.

cond-mat.mes-hall↗

arXiv2023

Impact of electrostatic crosstalk on spin qubits in dense CMOS quantum dot arrays

Quantum processors based on integrated nanoscale silicon spin qubits are a promising platform for highly scalable quantum computation. Current CMOS spin qubit processors consist of dense gate arrays to define the quantum dots, making them susceptible to crosstalk from capacitive coupling between a dot and its neighbouring gates. Small but sizeable spin-orbit interactions can transfer this electrostatic crosstalk to the spin g-factors, creating a dependence of the Larmor frequency on the electric field created by gate electrodes positioned even tens of nanometers apart. By studying the Stark shift from tens of spin qubits measured in nine different CMOS devices, we developed a theoretical frawework that explains how electric fields couple to the spin of the electrons in increasingly complex arrays, including those electric fluctuations that limit qubit dephasing times $T_2^*$. The results will aid in the design of robust strategies to scale CMOS quantum technology.

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