arXiv subjects

Petar Radojković

Publications and source records attributed to Petar Radojković.

4 recordsLinked to original sources

arXiv2026

Integration, Enhancements and Evaluation of Memory Simulators

Currently, there is no common methodology or set of practices for evaluating memory-system performance in integrated simulation infrastructures. As a result, studies adopt different evaluation approaches, which can lead to conflicting conclusions even for the same simulation infrastructure. We propose a validation methodology that evaluates memory-system performance from three complementary views: the memory simulator, the CPU--memory interface and the simulated application. We use these views to detect, understand and correct memory-simulation inaccuracies arising from simulator integration and simplified modeling of microarchitectural features. The methodology reveals that the application's perception of memory performance can become effectively decoupled from the detailed memory simulation. Most importantly, we identify and correct a fundamental memory-model mismatch between delayed-response cycle-accurate memory simulators and ZSim, a representative parallel CPU simulator. We demonstrate the broader applicability of these enhancements by applying them to ZSim integrations with Ramulator 2, DRAMsim3 and DRAMSys 4, covering all major public cycle-accurate memory simulators. After the corrections and enhancements, all integrations reproduce the main bandwidth--latency trends and key characteristics of the actual system. Across the evaluated simulators, STREAM bandwidth differs from actual-hardware measurements by less than 5% in most experiments, while pointer-chase latency remains 15--18% lower than on actual hardware. All simulator enhancements are released as open source.

cs.AR↗

arXiv2026

Performance and Energy Benefits of MRDIMMs

Multiplexed Rank DIMMs (MRDIMMs) have recently emerged as memory devices that enable higher bandwidth without increasing DRAM chip frequencies. This paper presents a detailed performance, power and energy evaluation of a production server with high-end MRDIMM main memory. The memory system upgrade from conventional registered DIMMs (RDIMMs) to MRDIMMs extends the bandwidth by 41% yielding 27-41% higher performance for bandwidth-bound workloads. Additionally, the latency improvement reaches hundreds of nanoseconds, benefiting a broad class of workloads sensitive to memory latency. At the same bandwidth utilization levels, RDIMMs and MRDIMMs exhibit similar power consumption. In the MRDIMM-extended bandwidth region, the performance improvements largely exceed the power increase, delivering up to 30% server energy savings for memory-bound workloads.

cs.AR↗

arXiv2024

DRAM Errors and Cosmic Rays: Space Invaders or Science Fiction?

It is widely accepted that cosmic rays are a plausible cause of DRAM errors in high-performance computing (HPC) systems, and various studies suggest that they could explain some aspects of the observed DRAM error behavior. However, this phenomenon is insufficiently studied in production environments. We analyze the correlations between cosmic rays and DRAM errors on two HPC clusters: a production supercomputer with server-class DDR3-1600 and a prototype with LPDDR3-1600 and no hardware error correction. Our error logs cover 2000 billion MB-hours for the MareNostrum 3 supercomputer and 135 million MB-hours for the Mont-Blanc prototype. Our analysis combines quantitative analysis, formal statistical methods and machine learning. We detect no indications that cosmic rays have any influence on the DRAM errors. To understand whether the findings are specific to systems under study, located at 100 meters above the sea level, the analysis should be repeated on other HPC clusters, especially the ones located on higher altitudes. Also, analysis can (and should) be applied to revisit and extend numerous previous studies which use cosmic rays as a hypothetical explanation for some aspects of the observed DRAM error behaviors.

cs.DC↗

arXiv2024

Reinforcement Learning-based Adaptive Mitigation of Uncorrected DRAM Errors in the Field

Scaling to larger systems, with current levels of reliability, requires cost-effective methods to mitigate hardware failures. One of the main causes of hardware failure is an uncorrected error in memory, which terminates the current job and wastes all computation since the last checkpoint. This paper presents the first adaptive method for triggering uncorrected error mitigation. It uses a prediction approach that considers the likelihood of an uncorrected error and its current potential cost. The method is based on reinforcement learning, and the only user-defined parameters are the mitigation cost and whether the job can be restarted from a mitigation point. We evaluate our method using classical machine learning metrics together with a cost-benefit analysis, which compares the cost of mitigation actions with the benefits from mitigating some of the errors. On two years of production logs from the MareNostrum supercomputer, our method reduces lost compute time by 54% compared with no mitigation and is just 6% below the optimal Oracle method. All source code is open source.

cs.DC↗