arXiv subjects

Pongstorn Maidee

Publications and source records attributed to Pongstorn Maidee.

3 recordsLinked to original sources

arXiv2026

Arcalís: Accelerating Remote Procedure Calls Using a Líghtweight Near-Cache Solution

Modern microservices increasingly depend on high-performance remote procedure calls (RPCs) to coordinate fine-grained, distributed computation. As network bandwidths continue to scale, the CPU overhead associated with RPC processing, particularly serialization, deserialization, and protocol handling, has become a critical bottleneck. This challenge is exacerbated by fast user-space networking stacks such as DPDK, which expose RPC processing as the dominant performance limiter. While prior hardware accelerators have explored NIC-attached and FPGA-based offload, these approaches remain farther from the cache hierarchy, so the frequent data accesses during RPC processing each pay an extra interconnect traversal cost that inflates RPC time. Therefore, RPC handling should occur as close as possible to the cache; however, a near-cache solution must be small, hence practical and deployable. Our key insight to enable such a solution is taking advantage of a reconfigurable accelerator that can be configured specifically for the services currently running on the CPUs. We present Arcal\'ıs, a near-cache RPC accelerator that positions a lightweight hardware engine adjacent to the last-level cache (LLC). Arcal\'ıs offloads RPC processing to dedicated microengines that operate with cache-line latency while preserving programmability. By decoupling RPC processing logic, enabling microservice-specific execution, and positioning itself near the LLC, Arcal\'ıs achieves a 1.72-4.91$\times$ end-to-end speedup compared to the CPU baseline, significantly reduces microarchitectural overhead by up to 88\%, and achieves up to a 1.62$\times$ higher throughput than prior solutions. These results highlight the potential of near-cache RPC acceleration as a practical solution for high-performance microservice deployment.

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arXiv2026

Pickle: Precise, Flexible Cross-Core Last-level Cache Data Prefetching for Irregular Memory Accesses

Graph analytics and sparse scientific workloads are dominated by parallel chains of data-dependent, long-latency memory accesses whose patterns are difficult for hardware to infer yet straightforward to express in software. Conventional hardware prefetchers attempt to recover this information from address streams alone, but false positives lead to substantial memory traffic overhead. Software-assisted approaches offer greater flexibility but still consume core limited resources. We propose Pickle, a software-defined, hardware-managed lastlevel cache (LLC) prefetcher that follows the decoupled access/execute philosophy. Pickle serves as an independent access engine, fully decoupled from core resources, that executes prefetch kernels sliced from the original application to bring data into the shared LLC ahead of demand. We evaluate Pickle using full-system, cycle-level simulation of a cluster of 8 high-performance cores, running all GAP benchmark suite algorithms across nine real-world graphs and irregular-access dominated scientific applications from the NAS parallel benchmark suite. Over a no-prefetching baseline, Pickle achieves 1.49x geomean speedup with only 2% DRAM traffic overhead on graph algorithms, and 1.53x with a 4.5% memory traffic reduction on NAS scatter/gather kernels. For reference, the state-of-the-art coreprivate indirect prefetcher achieves 1.40x but incurs 43% DRAM traffic overhead on graph workloads, and 1.36x at zero traffic overhead on scatter/gather kernels, illustrating the challenge of inferring irregular access patterns without application-level context. Pickle also composes transparently with private cache prefetchers: combining it with the state-of-the-art indirect or a simple stride prefetcher yields 1.65x-1.66x and 1.72x-1.84x geomean speedup on graph and NAS scatter/gather workloads, respectively.

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arXiv2025

Choreographer: A Full-System Framework for Fine-Grained Tasks in Cache Hierarchies

In this paper, we introduce Choreographer, a simulation framework that enables a holistic system-level evaluation of fine-grained accelerators designed for latency-sensitive tasks. Unlike existing frameworks, Choreographer captures all hardware and software overheads in core-accelerator and cache-accelerator interactions, integrating a detailed gem5-based hardware stack featuring an AMBA coherent hub interface (CHI) mesh network and a complete Linux-based software stack. To facilitate rapid prototyping, it offers a C++ application programming interface and modular configuration options. Our detailed cache model provides accurate insights into performance variations caused by cache configurations, which are not captured by other frameworks. The framework is demonstrated through two case studies: a data-aware prefetcher for graph analytics workloads, and a quicksort accelerator. Our evaluation shows that the prefetcher achieves speedups between 1.08x and 1.88x by reducing memory access latency, while the quicksort accelerator delivers more than 2x speedup with minimal address translation overhead. These findings underscore the ability of Choreographer to model complex hardware-software interactions and optimize performance in small task offloading scenarios.

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